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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id z11sm5527165wrh.70.2020.10.14.08.59.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Oct 2020 08:59:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1602691151; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HjmUmabdPFrqIWe27bV/PHgVzD7yxSTl/8t6QReuLlI=; b=QNdIfTr4fDgH4Apc9dXvVtJ62J+fHHhEu5HBKOElTZeVJBIvGxwibS7ZHAf2RfLTU/XBrY gfLpf5UrctJhPBFCYvLWF5L6CWuYGIjam9tiJrpBaxKyXx+jDA0QdyYismaLuL8BKJUesD ja6KvqlcI1bwV1r3UwEzmN1zHCYfmqc= X-MC-Unique: qK-0UsXINByTPMBqpXlWgA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HjmUmabdPFrqIWe27bV/PHgVzD7yxSTl/8t6QReuLlI=; b=Eo2B2lhz+/3TDYmNIt97PkEtGqjLe2YiCXDbaQqwW2ADuHIDZBE6SCHP10KZ7Y37X8 IdmFYzJF3f13Nm2xv3MxQmjfiTSNFFDEuEP6Dw+2Uulk5WFqf5htDGyRnyKLGM/zZU7i hAL+9PCExVLD9vXTBd7h0dy4gJX1AxWSFLRqX7yz65E9u7dOVkTKJjOtXyywttGWd5Av L2REOxq8yWahHq66JoZ08dLQilOPbHtLl4oswqWPXyZrpHk/v6QW+GI88ynwEP3A8zPQ UKLylxlKJf6IGKSy0TX5/FF2co3ZQ1w+iUilItjT394qruHQKCfTHjvla9pRFcjG9lWz epQw== X-Gm-Message-State: AOAM532Ny82DZhXFz5VfiU2SVuBeVsQawV4+1+EAJhZHxk7VHjYOWhd/ Ua1vRcIqhieSA6BMd5fYKnGdywAj43GIlZXK4a/4nJsduNaJn/vMFWR7b9vGv57hXcfiV0Jvr6G wqkokZBLXbU0hgg== X-Received: by 2002:a1c:9e0e:: with SMTP id h14mr141904wme.18.1602691147906; Wed, 14 Oct 2020 08:59:07 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyTCbHG7OyDh9+X4wwi0BcuIZEZiLxT8dDgXYokzetAJfBJy4+u1HRLfPIgjPrJGskXMtGz/A== X-Received: by 2002:a1c:9e0e:: with SMTP id h14mr141895wme.18.1602691147688; Wed, 14 Oct 2020 08:59:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Fam Zheng , Stefan Hajnoczi , Kevin Wolf , Max Reitz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 11/15] block/nvme: Trace controller capabilities Date: Wed, 14 Oct 2020 17:58:06 +0200 Message-Id: <20201014155810.102841-12-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201014155810.102841-1-philmd@redhat.com> References: <20201014155810.102841-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Controllers have different capabilities and report them in the CAP register. We are particularly interested by the page size limits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 10 ++++++++++ block/trace-events | 1 + 2 files changed, 11 insertions(+) diff --git a/block/nvme.c b/block/nvme.c index 11fba2d754d..fad727416ee 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -725,6 +725,16 @@ static int nvme_init(BlockDriverState *bs, const char = *device, int namespace, * Initialization". */ =20 cap =3D le64_to_cpu(regs->cap); + trace_nvme_controller_capability("Maximum Queue Entries Supported", + NVME_CAP_MQES(cap)); + trace_nvme_controller_capability("Contiguous Queues Required", + NVME_CAP_CQR(cap)); + trace_nvme_controller_capability("Subsystem Reset Supported", + NVME_CAP_NSSRS(cap)); + trace_nvme_controller_capability("Memory Page Size Minimum", + NVME_CAP_MPSMIN(cap)); + trace_nvme_controller_capability("Memory Page Size Maximum", + NVME_CAP_MPSMAX(cap)); if (!NVME_CAP_CSS(cap)) { error_setg(errp, "Device doesn't support NVMe command set"); ret =3D -EINVAL; diff --git a/block/trace-events b/block/trace-events index 6694c23e1c1..8a24d7a8650 100644 --- a/block/trace-events +++ b/block/trace-events @@ -134,6 +134,7 @@ qed_aio_write_postfill(void *s, void *acb, uint64_t sta= rt, size_t len, uint64_t qed_aio_write_main(void *s, void *acb, int ret, uint64_t offset, size_t le= n) "s %p acb %p ret %d offset %"PRIu64" len %zu" =20 # nvme.c +nvme_controller_capability(const char *desc, uint64_t value) "%s: %"PRIu64 nvme_kick(void *s, unsigned q_index) "s %p q #%u" nvme_dma_flush_queue_wait(void *s) "s %p" nvme_error(int cmd_specific, int sq_head, int sqid, int cid, int status) "= cmd_specific %d sq_head %d sqid %d cid %d status 0x%x" --=20 2.26.2