From nobody Thu May 9 22:54:08 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602610346; cv=none; d=zohomail.com; s=zohoarc; b=c0H6d54umgzgzV6ZemmDPFtKPZ1PCPuibr86gnEpq7B4R9yX8Zes0bT860SEPUQVtio/Ddsr8myI7wlfxj3SZBs7rt3dU8Py9LCUvb8ZisnfGWFZlikHkI3iLhHKMHvCXWDQOugxaad8tVwdnjz9nnKi8xlPDf7Whv53wws4xLo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602610346; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=BiAJfb1UlI6szU1qQF8cTz6vr/W08Xisf3DzldAD+Fk=; b=kmvyypt4d4Lp4MpWaHJrRlBqoWLbm1JiPOQRbTokMbnzTUaeNaAFiNwwcnPpblhV9Z8kYyZpj1d1wJg21zYWd75Uwwq3G4xwn+o3dqy2gD1pT8LVYrOmFNxVQ2gqy6wi+LN+G/dkakIOv0C8pbwzQmUqLFhOgC5YmVElvUrO/oc= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602610346534934.0488332627266; Tue, 13 Oct 2020 10:32:26 -0700 (PDT) Received: from localhost ([::1]:57518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kSO9x-0003eX-7G for importer@patchew.org; Tue, 13 Oct 2020 13:32:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40206) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kSO8e-0002gB-Lk; Tue, 13 Oct 2020 13:31:05 -0400 Received: from serv1.kernkonzept.com ([2a01:4f8:1c1c:b490::2]:43311 helo=mx.kernkonzept.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kSO8c-0002S3-Ni; Tue, 13 Oct 2020 13:31:04 -0400 Received: from [86.56.119.37] (helo=george-laptop.lan) by mx.kernkonzept.com with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) id 1kSO8Y-0000P0-Tb; Tue, 13 Oct 2020 19:30:58 +0200 From: Georg Kotheimer To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt Date: Tue, 13 Oct 2020 19:30:54 +0200 Message-Id: <20201013173054.451135-1-georg.kotheimer@kernkonzept.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: softfail client-ip=2a01:4f8:1c1c:b490::2; envelope-from=georg.kotheimer@kernkonzept.com; helo=mx.kernkonzept.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -7 X-Spam_score: -0.8 X-Spam_bar: / X-Spam_report: (-0.8 / 5.0 requ) BAYES_00=-1.9, KHOP_HELO_FCRDNS=0.4, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Georg Kotheimer Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The hstatus.GVA bit was not set if the faulting guest virtual address was zero. Signed-off-by: Georg Kotheimer Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 904899054d..c5852ce1b7 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -852,6 +852,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) bool async =3D !!(cs->exception_index & RISCV_EXCP_INT_FLAG); target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; target_ulong deleg =3D async ? env->mideleg : env->medeleg; + bool write_tval =3D false; target_ulong tval =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; @@ -873,6 +874,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + write_tval =3D true; tval =3D env->badaddr; break; default: @@ -904,7 +906,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong hdeleg =3D async ? env->hideleg : env->hedeleg; =20 if ((riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(env)) && tval) { + riscv_cpu_two_stage_lookup(env)) && write_tval) { /* * If we are writing a guest virtual address to stval, set * this to 1. If we are trapping to VS we will set this to= 0 --=20 2.25.1