From nobody Mon Feb 9 02:50:57 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1602565958; cv=none; d=zohomail.com; s=zohoarc; b=RG5Y4Yi+B6QaE3gMSJF6y/Yfe2K8Ij13jjz1AjiK+f42Ieqz0JK+GnMrvTr9nv5B2dfWItkgnlSB19PFEUe1Zq3Yp0P76OXG4X95lw3+j9BbLL7cR6OLdqi2ja7cO5sWIC2Ygp70g07oFHojilW1CEAwrd0/xRWtDQp3M/palLc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602565958; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=joEyn5u0NGUUQdYjSNmSW81bDsejqd4KYhcSeIJCEEE=; b=MUzHyaw45gxC8q2f9NZb2j2DmYgeYAuaU1bsjrDDnCAGUUiZpAppACYZ0xGj+FUprgu8QfSdVr0rezOZ/bsTAtm2lVw1E+wm0i8JpQGmnzcTd1lnAZZFeDNyDoA9EUhHaIWiLtg4OQ/jgww0WKu7s9MG1tBbV4jRvE8J/w9UcOo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602565958279420.57876077398714; Mon, 12 Oct 2020 22:12:38 -0700 (PDT) Received: from localhost ([::1]:41812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kSCc1-0003gL-4b for importer@patchew.org; Tue, 13 Oct 2020 01:12:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kSCa5-0001tt-6K for qemu-devel@nongnu.org; Tue, 13 Oct 2020 01:10:38 -0400 Received: from mga11.intel.com ([192.55.52.93]:57340) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kSCa3-0006XA-8T for qemu-devel@nongnu.org; Tue, 13 Oct 2020 01:10:36 -0400 Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2020 22:10:31 -0700 Received: from unknown (HELO local-michael-cet-test.sh.intel.com) ([10.239.159.128]) by fmsmga001.fm.intel.com with ESMTP; 12 Oct 2020 22:10:30 -0700 IronPort-SDR: RuFXXfI3foAmzN2uRkL2vjRzNCScb6fIN3kmdEdgohq7ybfji0ZA2YuzAt+a9LHr6rDc98l0mv MIBblPuUdQ6Q== X-IronPort-AV: E=McAfee;i="6000,8403,9772"; a="162385621" X-IronPort-AV: E=Sophos;i="5.77,369,1596524400"; d="scan'208";a="162385621" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: 34n4gzA3JmH9QkYAdf7ZITO/qCENxWrCtaurDREGNoIjNsXn1IDCzbGNaLWGaRmvDWpvwpfDlD LsZfagbDLWEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,369,1596524400"; d="scan'208";a="420427124" From: Yang Weijiang To: pbonzini@redhat.com, mtosatti@redhat.com, rth@twiddle.net, ehabkost@redhat.com, sean.j.christopherson@intel.com, qemu-devel@nongnu.org Subject: [Qemu-devel][PATCH v6 3/6] x86/cpu: Enable CET components support for XSAVE Date: Tue, 13 Oct 2020 13:19:32 +0800 Message-Id: <20201013051935.6052-4-weijiang.yang@intel.com> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20201013051935.6052-1-weijiang.yang@intel.com> References: <20201013051935.6052-1-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.93; envelope-from=weijiang.yang@intel.com; helo=mga11.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/13 01:10:25 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang , hao.wu@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" CET Shadow Stack(SHSTK) and Indirect Branch Tracking(IBT) are enumerated via CPUID.(EAX=3D07H,ECX=3D0H):ECX[bit 7] and EDX[bit 20] respectively. Two CET bits (bit 11 and 12) are defined in MSR_IA32_XSS for XSAVE. They correspond to CET states in user and supervisor mode respectively. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 18 ++++++++++++++++++ target/i386/cpu.h | 23 ++++++++++++++++++++++- 2 files changed, 40 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 38eab02b3d..5496fd68d4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1071,6 +1071,16 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, [FEAT_XSAVE_XSS_LO] =3D { .type =3D CPUID_FEATURE_WORD, + .feat_names =3D { + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "cet-u", + "cet-s", NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + }, .cpuid =3D { .eax =3D 0xD, .needs_ecx =3D true, @@ -1497,6 +1507,14 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .offset =3D offsetof(X86XSaveArea, pkru_state), .size =3D sizeof(XSavePKRU) }, + [XSTATE_CET_U_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0, + .size =3D sizeof(XSavesCETU) }, + [XSTATE_CET_S_BIT] =3D { + .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_CET_SHSTK, + .offset =3D 0, + .size =3D sizeof(XSavesCETS) }, }; =20 static uint32_t xsave_area_size(uint64_t mask) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 10bf4d8b51..d4563fa0e8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -493,6 +493,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_CET_U_BIT 11 +#define XSTATE_CET_S_BIT 12 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -503,6 +505,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_CET_U_MASK (1ULL << XSTATE_CET_U_BIT) +#define XSTATE_CET_S_MASK (1ULL << XSTATE_CET_S_BIT) =20 /* CPUID feature bits available in XCR0 */ #define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ @@ -512,7 +516,7 @@ typedef enum X86Seg { XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) =20 /* CPUID feature bits available in XSS */ -#define CPUID_XSTATE_XSS_MASK 0 +#define CPUID_XSTATE_XSS_MASK (XSTATE_CET_U_MASK) =20 /* CPUID feature words */ typedef enum FeatureWord { @@ -760,6 +764,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_WAITPKG (1U << 5) /* Additional AVX-512 Vector Byte Manipulation Instruction */ #define CPUID_7_0_ECX_AVX512_VBMI2 (1U << 6) +/* CET SHSTK feature */ +#define CPUID_7_0_ECX_CET_SHSTK (1U << 7) /* Galois Field New Instructions */ #define CPUID_7_0_ECX_GFNI (1U << 8) /* Vector AES Instructions */ @@ -795,6 +801,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_SERIALIZE (1U << 14) /* TSX Suspend Load Address Tracking instruction */ #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) +/* CET IBT feature */ +#define CPUID_7_0_EDX_CET_IBT (1U << 20) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ @@ -1285,6 +1293,19 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 11: User mode CET state */ +typedef struct XSavesCETU { + uint64_t u_cet; + uint64_t user_ssp; +} XSavesCETU; + +/* Ext. save area 12: Supervisor mode CET state */ +typedef struct XSavesCETS { + uint64_t kernel_ssp; + uint64_t pl1_ssp; + uint64_t pl2_ssp; +} XSavesCETS; + typedef struct X86XSaveArea { X86LegacyXSaveArea legacy; X86XSaveHeader header; --=20 2.26.2