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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y66sm7095961wmd.14.2020.10.12.08.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:37:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=karobGThPUBbxRoaP+yKeLZSzAdIl7EhuaiEL3CMR4I=; b=pB1gdTf6L1Hy1roe0BRvGPb8EXrIBhUrtaB+/QVj4KAv+etAljPqtZ+CMfpTatXXU5 PTCmXyMsX4aaf0l5BqBHW3kztsLnAOd0qVsOhcIJ0kUzwZwYjF2BAat89k0XWk5ACnRU vQwGt3Jd5J5kRjfQyj1M7VDXP2S3XSngTGcFG1iu15ss+s2O0e5LuMg7i0BSrxFoZrwO uQ1mZ6k/zJAUJMNtX14faQ8iU6zgvT5mSMTNIQahGmw7BwHjH4gbMQ/WpTEJ3MwWYD8b 26SA9d9tEDuDqk/0WZIKLXnByjvlbI7a2HwilvbrUWVGqjsg7LtsrBjXe3Hb4b8zOaa7 y6Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=karobGThPUBbxRoaP+yKeLZSzAdIl7EhuaiEL3CMR4I=; b=oPkbPk5oj28gRTecpwMUWlR6G9kNP1JeD+zO5GECl8e00vL6osgQvz/07979FR23uh JZ6Ks5d6sGBcOBsjGiV1g50oFR8VyL0Qk2jqUbb9U2UXzvAsmKr5oHUUTvVjNb8pMXgk J/UPjCMMgIVhnzZmSNKfT0d8CP8eNPs+zLjBVD5nnfUm5vZrHum1E3dj+2HEBUBevoRv CR4WO3n7jTr1gPT6syatRB31bXi5NoaF+OZ44kaPcstlZplmjErLifA2EDn8P2Gm3C2R LWpE75b4gPaMLaBIQsBb4olXK5TR6/ETIwB64y+/vsUVbrIU1IQhvUyEhJJfuIOKq/jN 3AfQ== X-Gm-Message-State: AOAM533jKl93esov9eKo+cFTYnLdY6TJzHpZZGnlB9eGQ6Mnx3r/MNoA GatAgqvmH1z/bM562KJX0DVu+Q== X-Google-Smtp-Source: ABdhPJw0Am8eqctO9howY6+TfcneaCBHujPTjQeL4K6ppinePQxEQ0slLXi2xPwIWrng9xOPQ9FQjw== X-Received: by 2002:a1c:5a06:: with SMTP id o6mr11718388wmb.181.1602517077201; Mon, 12 Oct 2020 08:37:57 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 08/10] target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile Date: Mon, 12 Oct 2020 16:37:44 +0100 Message-Id: <20201012153746.9996-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153746.9996-1-peter.maydell@linaro.org> References: <20201012153746.9996-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we squash the ID register fields so that we don't advertise it to the guest. This code was written for A-profile and needs some tweaks to work correctly on M-profile: * A-profile only fields should not be zeroed on M-profile: - MVFR0.FPSHVEC,FPTRAP - MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP - MVFR2.SIMDMISC * M-profile only fields should be zeroed on M-profile: - MVFR1.FP16 In particular, because MVFR1.SIMDHP on A-profile is the same field as MVFR1.FP16 on M-profile this code was incorrectly disabling FP16 support on an M-profile CPU (where has_neon is always false). This isn't a visible bug yet because we don't have any M-profile CPUs with FP16 support, but the change is necessary before we introduce any. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 29 ++++++++++++++++++----------- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 056319859fb..186ee621a65 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1429,17 +1429,22 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, FPSP, 0); u =3D FIELD_DP32(u, MVFR0, FPDP, 0); - u =3D FIELD_DP32(u, MVFR0, FPTRAP, 0); u =3D FIELD_DP32(u, MVFR0, FPDIVIDE, 0); u =3D FIELD_DP32(u, MVFR0, FPSQRT, 0); - u =3D FIELD_DP32(u, MVFR0, FPSHVEC, 0); u =3D FIELD_DP32(u, MVFR0, FPROUND, 0); + if (!arm_feature(env, ARM_FEATURE_M)) { + u =3D FIELD_DP32(u, MVFR0, FPTRAP, 0); + u =3D FIELD_DP32(u, MVFR0, FPSHVEC, 0); + } cpu->isar.mvfr0 =3D u; =20 u =3D cpu->isar.mvfr1; u =3D FIELD_DP32(u, MVFR1, FPFTZ, 0); u =3D FIELD_DP32(u, MVFR1, FPDNAN, 0); u =3D FIELD_DP32(u, MVFR1, FPHP, 0); + if (arm_feature(env, ARM_FEATURE_M)) { + u =3D FIELD_DP32(u, MVFR1, FP16, 0); + } cpu->isar.mvfr1 =3D u; =20 u =3D cpu->isar.mvfr2; @@ -1475,16 +1480,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) u =3D FIELD_DP32(u, ID_ISAR6, FHM, 0); cpu->isar.id_isar6 =3D u; =20 - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, SIMDLS, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); - cpu->isar.mvfr1 =3D u; + if (!arm_feature(env, ARM_FEATURE_M)) { + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, SIMDLS, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); + u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); + cpu->isar.mvfr1 =3D u; =20 - u =3D cpu->isar.mvfr2; - u =3D FIELD_DP32(u, MVFR2, SIMDMISC, 0); - cpu->isar.mvfr2 =3D u; + u =3D cpu->isar.mvfr2; + u =3D FIELD_DP32(u, MVFR2, SIMDMISC, 0); + cpu->isar.mvfr2 =3D u; + } } =20 if (!cpu->has_neon && !cpu->has_vfp) { --=20 2.20.1