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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y66sm7095961wmd.14.2020.10.12.08.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:37:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=73sxXQONcqBgzHuOsaIz5hu+3BY6+pw52N6WyKkQfZo=; b=exgSCy6TBYKs+2u6PmauhdJ/pAV+QrSf2WLOJjFOA913gOLmL4t0hjV+pGDqFu59Kd shf6GEjbd5Xl9baMOMbtewoojWiuyQ1lZCErfoS3kXKtI3bWXD0olSbRYV1TsabJX/7q /JuIkVjG6Wj0oH+m7Hk+KEq52DO13lKiXQ3MhV9kMny4wRJLcVNJKKEYWo7aMIIHMgKm segKFQ8AK/ZTWrMvOWZZ5NaPOdnIwXzrtWxUQK93fM2sNdnX5MQk2hpbZi2DEOOt3eTq hyuH9Qv3WwK2VwWEQ+vSoTrHi/uqU8HHczSgqEPivdBX+3weH2MjPpKUR4hMhd334SB3 9R6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=73sxXQONcqBgzHuOsaIz5hu+3BY6+pw52N6WyKkQfZo=; b=iBnKR604NRohEYj6AkWjhObOmjd68x5p1w1bFNsZb78CfjJ9EYqwJr5mVHejiiKeC/ CCfi8gCIh/kohLIpji4MLt23jH+IZyHya2Mh3gm+yS548hr79cM7KOFniNZ6jiY1EZVh BpxBIP5pgJUDuTLpuyzg6lmnT/ctMfO599pm0xeFK7u/GX/q5fRR+l9iQ/RlNApSvYUl tqxcv9YhX+gDA9XrCWBkDw0Yl3pkNn5ZSrmzYIaUpeojpLGR15Y4GCeCzzcj2ySXcaUE Xzo5MuhZZzNqHHbCNWYGINlB5SPDEF56cQ+d1nBNFLFfMoWAu79Hxj1Ah5+saAEtLDTz jXpw== X-Gm-Message-State: AOAM5336GovaUJOtiCA705XHhhdmk5Sl7rxf/87NsFX9OTuOBVh81B4z jhChRXurwVfbEx81kHQiqmgySw== X-Google-Smtp-Source: ABdhPJy4LPQpvrsnt5RCAZ9vHcRDudF9jd0mi6uJSyVW1oujaQiAGY70CcWC3vHFoJMgAPKgVLa9yQ== X-Received: by 2002:a1c:1f89:: with SMTP id f131mr11867963wmf.10.1602517070880; Mon, 12 Oct 2020 08:37:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 02/10] target/arm: Implement v8.1M NOCP handling Date: Mon, 12 Oct 2020 16:37:38 +0100 Message-Id: <20201012153746.9996-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153746.9996-1-peter.maydell@linaro.org> References: <20201012153746.9996-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From v8.1M, disabled-coprocessor handling changes slightly: * coprocessors 8, 9, 14 and 15 are also governed by the cp10 enable bit, like cp11 * an extra range of instruction patterns is considered to be inside the coprocessor space We previously marked these up with TODO comments; implement the correct behaviour. Unfortunately there is no ID register field which indicates this behaviour. We could in theory test an unrelated ID register which indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch >=3D 3 (low-overhead-loops), but it seems better to simply define a new ARM_FEATURE_V8_1M feature flag and use it for this and other new-in-v8.1M behaviour that isn't identifiable from the ID registers. Signed-off-by: Peter Maydell --- target/arm/cpu.h | 1 + target/arm/m-nocp.decode | 10 ++++++---- target/arm/translate-vfp.c.inc | 17 +++++++++++++++-- 3 files changed, 22 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfff1b5c8fe..74392fa0295 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1985,6 +1985,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_M_MAIN, /* M profile Main Extension */ + ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */ }; =20 static inline int arm_feature(CPUARMState *env, int feature) diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode index 7182d7d1217..28c8ac6b94c 100644 --- a/target/arm/m-nocp.decode +++ b/target/arm/m-nocp.decode @@ -29,14 +29,16 @@ # If the coprocessor is not present or disabled then we will generate # the NOCP exception; otherwise we let the insn through to the main decode. =20 +&nocp cp + { # Special cases which do not take an early NOCP: VLLDM and VLSTM VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 # TODO: VSCCLRM (new in v8.1M) is similar: #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0 =20 - NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- - NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- - # TODO: From v8.1M onwards we will also want this range to NOCP - #NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- cp=3D10 + NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp + NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp + # From v8.1M onwards this range will also NOCP: + NOCP_8_1 111- 1111 ---- ---- ---- ---- ---- ---- &nocp cp=3D10 } diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc index 28e0dba5f14..cc9ffb95887 100644 --- a/target/arm/translate-vfp.c.inc +++ b/target/arm/translate-vfp.c.inc @@ -3459,7 +3459,7 @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VL= LDM_VLSTM *a) return true; } =20 -static bool trans_NOCP(DisasContext *s, arg_NOCP *a) +static bool trans_NOCP(DisasContext *s, arg_nocp *a) { /* * Handle M-profile early check for disabled coprocessor: @@ -3472,7 +3472,11 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a) if (a->cp =3D=3D 11) { a->cp =3D 10; } - /* TODO: in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable= */ + if (arm_dc_feature(s, ARM_FEATURE_V8_1M) && + (a->cp =3D=3D 8 || a->cp =3D=3D 9 || a->cp =3D=3D 14 || a->cp =3D= =3D 15)) { + /* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */ + a->cp =3D 10; + } =20 if (a->cp !=3D 10) { gen_exception_insn(s, s->pc_curr, EXCP_NOCP, @@ -3489,6 +3493,15 @@ static bool trans_NOCP(DisasContext *s, arg_NOCP *a) return false; } =20 +static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a) +{ + /* This range needs a coprocessor check for v8.1M and later only */ + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { + return false; + } + return trans_NOCP(s, a); +} + static bool trans_VINS(DisasContext *s, arg_VINS *a) { TCGv_i32 rd, rm; --=20 2.20.1