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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y10sm19675284wrq.73.2020.10.12.08.34.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:34:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m+57w4waUDsMvpjTdXukUzVLKUiAH7ggRqO2IkZWWK8=; b=glkg0HcRhX7qs2EfhByu9sLqzsZG+NVIzN3ASb+5El6+xbkwltqLZBQ9y7QDt9Q3+t IKSW0n/+zZDYpK8TYI1usseAQtJ8+Lg4kk5VA5aW944p/mOzdJeudrY+vVYMxRDrQTR0 EZqJIeHtDPkeOZ+z/I2g/c3LppkiHOarGOCaeULvlHeQl3xjY7Hzl/JLxX3HEFWs5A0Q 71cDTJNSef42GXUBp33nfpDGxweSrvKsDM61EJVmgc+X6FouxzUwy7FfMAcHXp5XE3+L dxjjmhTe64fo2F0VcAd4lZ3seZAUWld1go6uyPeiFvPc2KBTDcGRSU42VrKCUp2pNQF4 +SwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m+57w4waUDsMvpjTdXukUzVLKUiAH7ggRqO2IkZWWK8=; b=WYXckgnkxi3EuvI2vrC0qOjByaUeR9y9qGAzkjnu9ni9a1KprYBox4RZdNKU9zvMG1 omI/2u716f5QZPuggHzKpvRIiqT+p64uqr6EF8YEKymVeehqDNnRuuxSdVP8YJpD/sV0 nUqSawcpEkQX0fsJScfSelKGy7JbTGF/HHhsGU789NtNzKJtOUr+FFKHHXOD4xR8Hq58 ZY0FUszvD6uX76tfH3DnD5wXI+zx8Sxj+IashNfYbZbBX9bCg9NCAqIDmbX0lH93fZlw tCYB4xUqOu5U1ybkCpld8wcAmF1OBcJpbwkZ0KPNxt7npmTCBKwM7vP//Ebz8lxl/7Nj t13Q== X-Gm-Message-State: AOAM530mAPZMcrfSnKWll2Q8euZqZ3IRB2auK9fosWQUHUBd9CO9+eTY snrPG58JFLrxwjlm/htKI/fccg== X-Google-Smtp-Source: ABdhPJy0s/tMr7a7W6VpAEx1VMxi0ETX8ZpI/O5OuEUPxNi5OepY7TXj7Y4dhULZEvAW6rRj4kdY4A== X-Received: by 2002:a7b:cb82:: with SMTP id m2mr12017658wmi.56.1602516870030; Mon, 12 Oct 2020 08:34:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] hw/intc/arm_gicv3_cpuif: Make GIC maintenance interrupts work Date: Mon, 12 Oct 2020 16:33:40 +0100 Message-Id: <20201012153408.9747-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153408.9747-1-peter.maydell@linaro.org> References: <20201012153408.9747-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt into the GICv3CPUState struct's maintenance_irq field. This will only work if the board happens to have already wired up the CPU maintenance IRQ before the GIC was realized. Unfortunately this is not the case for the 'virt' board, and so the value that gets copied is NULL (since a qemu_irq is really a pointer to an IRQState struct under the hood). The effect is that the CPU interface code never actually raises the maintenance interrupt line. Instead, since the GICv3CPUState has a pointer to the CPUState, make the dereference at the point where we want to raise the interrupt, to avoid an implicit requirement on board code to wire things up in a particular order. Reported-by: Jose Martins Signed-off-by: Peter Maydell --- QEMU's implementation here is a bit odd because we've put all the logic into the "GIC" device where in real hardware it's split between a GIC device and the CPU interface part in the CPU. If we had arranged it in that way then we wouldn't have this odd bit of code where the GIC device needs to raise an IRQ line that belongs to the CPU. Not sure why we've never noticed this bug previously with KVM as a guest, you'd think we'd have spotted "maintenance interrupts just don't work"... --- include/hw/intc/arm_gicv3_common.h | 1 - hw/intc/arm_gicv3_cpuif.c | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 0331b0ffdb8..91491a2f664 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -153,7 +153,6 @@ struct GICv3CPUState { qemu_irq parent_fiq; qemu_irq parent_virq; qemu_irq parent_vfiq; - qemu_irq maintenance_irq; =20 /* Redistributor */ uint32_t level; /* Current IRQ level */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 08e000e33c6..43ef1d7a840 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -399,6 +399,7 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) int irqlevel =3D 0; int fiqlevel =3D 0; int maintlevel =3D 0; + ARMCPU *cpu =3D ARM_CPU(cs->cpu); =20 idx =3D hppvi_index(cs); trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); @@ -424,7 +425,7 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) =20 qemu_set_irq(cs->parent_vfiq, fiqlevel); qemu_set_irq(cs->parent_virq, irqlevel); - qemu_set_irq(cs->maintenance_irq, maintlevel); + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); } =20 static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2624,8 +2625,6 @@ void gicv3_init_cpuif(GICv3State *s) && cpu->gic_num_lrs) { int j; =20 - cs->maintenance_irq =3D cpu->gicv3_maintenance_interrupt; - cs->num_list_regs =3D cpu->gic_num_lrs; cs->vpribits =3D cpu->gic_vpribits; cs->vprebits =3D cpu->gic_vprebits; --=20 2.20.1