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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y10sm19675284wrq.73.2020.10.12.08.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:34:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xCPWjLYyI6z3WFhhXaeYUbi5QZIddcoWl6SEfIfuuFs=; b=jvkUIDRClN9EIrNy2RSdtWRPqcJKUB35LA78DZJ65CbJFay23p7wAmAtvMRKkwVIpq j0+GyMO3ekHx2NzlGH+Hu9wWt9FXxGLOUkDTVSKRJa0NV/JNJ9ggidTuULb8wMRJ1PPT 8eJ07v5t77Q1eUb58VmOQX+TU6wbNttw1+v5rer4GpwhucVMJ8ppyh7oqaDwHEQQwvSa vyOaQVcjZeJsj9ggOBzoUk6D+QaRVIuPWHun2LKlWMnRvw0wfedq0OK5F85MgWPP7xMi T7iUDyv0Lo5qbZklcQQuOjlmBAkxZeNcK4t24SC0U7TEOGkq85EDlnUvHflXkC96g78r q4eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xCPWjLYyI6z3WFhhXaeYUbi5QZIddcoWl6SEfIfuuFs=; b=QdEFd5QiXCQFU50kDamTGDLNWXokoxTqJ9Hkbl2Z86TmxfItOBOyWvi9JqBVNO+Zoz ogCOEVtDFz/DoPt9YRc0R8Bl+rH839loBKyC6Qs0RWxjBzLCwuwVr1aSZM7BgJcEQSeF Y/uk3eN7FqG0x2X6XFEAq8rZjjJP7MhWNVeJFZapL615IZjNt4VBasNPMdLWdazQy3gd qZ3Re2yzADyGxGxScO3r37Q3aRKiVVgh7K5a9guIiLtyRLi6RegVU8SJ1fU7Vq/y5vR5 bz3HSDBxJbxqcTw+08W5/7bSNQSbDjbeJWqqfTxVsV2MK3YR7CABi/ZYCxqWEsiNx0f4 UmFg== X-Gm-Message-State: AOAM532f85ZdGYCu8HDTvAsRRczvHIyAv3/SRZDxwA4/5C5JV4XpVxtL eBeQVUPFpDqPzsRcL3trapsvWQ== X-Google-Smtp-Source: ABdhPJw3rY3457BdxkO9G6YrxPMZWwl0qoCALdW6L3/dAggIH2iCcdauht8QaOmIHyjCkS2KNOMngQ== X-Received: by 2002:adf:f841:: with SMTP id d1mr20555398wrq.297.1602516869112; Mon, 12 Oct 2020 08:34:29 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] hw/intc/arm_gicv3_cpuif: Don't copy CPU's maintenance interrupt Date: Mon, 12 Oct 2020 16:33:39 +0100 Message-Id: <20201012153408.9747-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153408.9747-1-peter.maydell@linaro.org> References: <20201012153408.9747-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In gicv3_init_cpuif() we copy the ARMCPU gicv3_maintenance_interrupt into the GICv3CPUState struct's maintenance_irq field. This will only work if the board happens to have already wired up the CPU maintenance IRQ before the GIC was realized. Unfortunately this is not the case for the 'virt' board, and so the value that gets copied is NULL (since a qemu_irq is really a pointer to an IRQState struct under the hood). The effect is that the CPU interface code never actually raises the maintenance in2Dterrupt line. Instead, since the GICv3CPUState has a pointer to the CPUState, make the dereference at the point where we want to raise the interrupt, to avoid an implicit requirement on board code to wire things up in a particular order. Reported-by: Jose Martins Signed-off-by: Peter Maydell --- QEMU's implementation here is a bit odd because we've put all the logic into the "GIC" device where in real hardware it's split between a GIC device and the CPU interface part in the CPU. If we had arranged it in that way then we wouldn't have this odd bit of code where the GIC device needs to raise an IRQ line that belongs to the CPU. Not sure why we've never noticed this bug previously with KVM as a guest, you'd think we'd have spotted "maintenance interrupts just don't work"... --- include/hw/intc/arm_gicv3_common.h | 1 - hw/intc/arm_gicv3_cpuif.c | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 0331b0ffdb8..91491a2f664 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -153,7 +153,6 @@ struct GICv3CPUState { qemu_irq parent_fiq; qemu_irq parent_virq; qemu_irq parent_vfiq; - qemu_irq maintenance_irq; =20 /* Redistributor */ uint32_t level; /* Current IRQ level */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 08e000e33c6..43ef1d7a840 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -399,6 +399,7 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) int irqlevel =3D 0; int fiqlevel =3D 0; int maintlevel =3D 0; + ARMCPU *cpu =3D ARM_CPU(cs->cpu); =20 idx =3D hppvi_index(cs); trace_gicv3_cpuif_virt_update(gicv3_redist_affid(cs), idx); @@ -424,7 +425,7 @@ static void gicv3_cpuif_virt_update(GICv3CPUState *cs) =20 qemu_set_irq(cs->parent_vfiq, fiqlevel); qemu_set_irq(cs->parent_virq, irqlevel); - qemu_set_irq(cs->maintenance_irq, maintlevel); + qemu_set_irq(cpu->gicv3_maintenance_interrupt, maintlevel); } =20 static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2624,8 +2625,6 @@ void gicv3_init_cpuif(GICv3State *s) && cpu->gic_num_lrs) { int j; =20 - cs->maintenance_irq =3D cpu->gicv3_maintenance_interrupt; - cs->num_list_regs =3D cpu->gic_num_lrs; cs->vpribits =3D cpu->gic_vpribits; cs->vprebits =3D cpu->gic_vprebits; --=20 2.20.1