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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id y10sm19675284wrq.73.2020.10.12.08.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2020 08:34:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Rr+JVKyDamSf0xBTUVSv5bImqBYLa2yDIIfkheqLG6Y=; b=NSdGchXobLRvobB1cyetRRAvSm9hlhgg/38eE/ovGE8IFh5XCOQ9xlqpkKyEoa7omY zQsoAjBTSRQqpwyqI+awAvrbM1OFAiOzg6cG2KkCBGvLMbJWeIQ9bsHpoldfWUgSpve5 6WY3s9keximJhZ2tWZO0fxygF64LdXfzFy8iRdjKslyBChTU+RtbWJ35GH4KoJ6P6kAy 9vtE9Jn1wnky3wzp3o7SOl0MptJNsFI4CdkGAguuDv/tsXIVLwQSEhO46ej5ZMtLKa/l 24VC5Hy1O3vkGnt+ZAlnTmCU2gIbBAnA74TeLtxPSra76N7wh5pUtIlTdhoUTXE9ixAW lW2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Rr+JVKyDamSf0xBTUVSv5bImqBYLa2yDIIfkheqLG6Y=; b=GLgd25UEZS0AkIvQuzEPbZF6FFGfDd7Pl0uFAGlm2jg4c7Mgu3UeoPYEXR+Dd51K0N AEpITTSOiKOtlvNLkAA9u94TCK8WPCfgAhUXrMsqXU3ocIKszaXEDvkBEuSufKRNX5jG ayskeLoIDTFgVKouNps4zxqAhsJ9bvweG/YlIRJEeCrl2c7tQVQEE4gYMbe9dQmOc1od mTjVuwp5nAOpRX1tqV0miomMD6B8M2ag6IkUs5UG3r80EhRXQhd6qFf1bYPL4gLE7YNq db69tHaljpz1n8noDIBWpiEECsiLX3oXEGrwdytEwEvA5JynJWKuCM7Qx/BUmfRgXK1r 2qaQ== X-Gm-Message-State: AOAM533DkAiccoIFK8aoKzfhM9XH1m3d3nyVYl7WfWYnuQq9CB+qIxZ4 UgLfr+H/DoNHLI7e+QiwHwNoUA== X-Google-Smtp-Source: ABdhPJyoSC+UENnYPxUAoh2yzfjG7NREqu6kj3+HPN+qnsGErRyvtjE6dJDKeJ9lcfsb3H/t519vqw== X-Received: by 2002:a5d:5482:: with SMTP id h2mr21046891wrv.165.1602516863094; Mon, 12 Oct 2020 08:34:23 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] hw/arm/mps2: New board model mps2-386 Date: Mon, 12 Oct 2020 16:33:34 +0100 Message-Id: <20201012153408.9747-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201012153408.9747-1-peter.maydell@linaro.org> References: <20201012153408.9747-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell --- hw/arm/mps2.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 9f12934ca8f..559b297e788 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -15,6 +15,7 @@ * as seen by the guest depend significantly on the FPGA image. * We model the following FPGA images: * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 + * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 * * Links to the TRM for the board itself and to the various Application @@ -47,6 +48,7 @@ =20 typedef enum MPS2FPGAType { FPGA_AN385, + FPGA_AN386, FPGA_AN511, } MPS2FPGAType; =20 @@ -79,6 +81,7 @@ typedef struct { =20 #define TYPE_MPS2_MACHINE "mps2" #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") +#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386") #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") =20 #define MPS2_MACHINE(obj) \ @@ -142,7 +145,7 @@ static void mps2_common_init(MachineState *machine) * * Common to both boards: * 0x21000000..0x21ffffff : PSRAM (16MB) - * AN385 only: + * AN385/AN386 only: * 0x00000000 .. 0x003fffff : ZBT SSRAM1 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 @@ -157,7 +160,7 @@ static void mps2_common_init(MachineState *machine) * 0x20000000 .. 0x2001ffff : SRAM * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 * - * The AN385 has a feature where the lowest 16K can be mapped + * The AN385/AN386 has a feature where the lowest 16K can be mapped * either to the bottom of the ZBT SSRAM1 or to the block RAM. * This is of no use for QEMU so we don't implement it (as if * zbt_boot_ctrl is always zero). @@ -166,6 +169,7 @@ static void mps2_common_init(MachineState *machine) =20 switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400= 000); make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); @@ -193,6 +197,7 @@ static void mps2_common_init(MachineState *machine) armv7m =3D DEVICE(&mms->armv7m); switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: @@ -229,6 +234,7 @@ static void mps2_common_init(MachineState *machine) =20 switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: { /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. @@ -380,7 +386,7 @@ static void mps2_common_init(MachineState *machine) */ lan9118_init(&nd_table[0], 0x40200000, qdev_get_gpio_in(armv7m, - mmc->fpga_type =3D=3D FPGA_AN385 ? 13 : = 47)); + mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 @@ -409,6 +415,17 @@ static void mps2_an385_class_init(ObjectClass *oc, voi= d *data) mmc->scc_id =3D 0x41043850; } =20 +static void mps2_an386_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS2 with AN386 FPGA image for Cortex-M4"; + mmc->fpga_type =3D FPGA_AN386; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + mmc->scc_id =3D 0x41043860; +} + static void mps2_an511_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -435,6 +452,12 @@ static const TypeInfo mps2_an385_info =3D { .class_init =3D mps2_an385_class_init, }; =20 +static const TypeInfo mps2_an386_info =3D { + .name =3D TYPE_MPS2_AN386_MACHINE, + .parent =3D TYPE_MPS2_MACHINE, + .class_init =3D mps2_an386_class_init, +}; + static const TypeInfo mps2_an511_info =3D { .name =3D TYPE_MPS2_AN511_MACHINE, .parent =3D TYPE_MPS2_MACHINE, @@ -445,6 +468,7 @@ static void mps2_machine_init(void) { type_register_static(&mps2_info); type_register_static(&mps2_an385_info); + type_register_static(&mps2_an386_info); type_register_static(&mps2_an511_info); } =20 --=20 2.20.1