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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id n9sm22111984wrq.72.2020.10.11.12.49.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2020 12:49:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/fQo3DSJb6riAH6KnfckECiEhkMalNL1pPpYvWlbzCc=; b=fchLa3yE6WsO/FZ+TB5rqAIHERo2Wc0kfScuX4Nd1FAJjMJybOer7ydG7VO4fPRhUM byTxfmCYAFwlw73VF3USnknTVXPX77Ml+HloAqCxwp4ZRiFf1eaa6cQVpUE7nHAVewzR 2CICmGkLiY4fFTNAJcbjESHcyfORodUgr0ysfOzyI+XkeKB71lBmGoa6UsH0ozKWU7+Z ba639AW3CwlVdXtlEaaWUuFPcu/31i7bjxPW7ZIPXVpEB0PNcJUXdx9+aJ78uDX3L32M jnTT8a+bBoE2urRl3hVdSj1VuXC0SuWxuyEmpYtRxmRfu8SnnHw4VEPkbpFhWJyU409A 3Z2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=/fQo3DSJb6riAH6KnfckECiEhkMalNL1pPpYvWlbzCc=; b=W4RhwBcUL8jD3s6VPfaFxtrFOfPxFRNLz+O1DO1MUYqmNls2vPxr9OGPcIuDXArfSg I4XzdJQetK3OdnauAFz7z4Il0B5R7O0E2mfdxSvERablcuPR/DeKXtc7UF9IZZCwrUwq PVOC25DFTPFaZ1cRKJlC+WnsGoUD++jABSjgcc3kYsrwfG8j8fe4psaDKFaUtCRs3Rs/ mRTrRQw0PEA8xCU8SJWHWf9SoDl4zzTUdCSaBArXtMBIn79YaLuDjPbKHxDo0ryhXo/V 2N+Y1WNjcIkqboqKmkzlguuiK9b7pXNvdMf6g9nr0jT2nTDyX6SgQo7+5dZpruYO/RW8 uvcw== X-Gm-Message-State: AOAM533a0Mkv8Kld/xRsd4TEKp8n/ShMXVtFXU7zssvXgGLUmFi66yuO lPS/zg0nEpgLVniRtoxKyGg= X-Google-Smtp-Source: ABdhPJz6A99BRgIPa/1KR4ERdM5WL50IzAC2V7BytlJ8nFXrdYBkI/cd6vxwEbPTmcgpngPy+W2cgw== X-Received: by 2002:a1c:9949:: with SMTP id b70mr7946954wme.116.1602445765529; Sun, 11 Oct 2020 12:49:25 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: "Michael S. Tsirkin" , Aleksandar Rikalo , Peter Maydell , Aurelien Jarno , Jiaxun Yang , Paolo Bonzini , Thomas Huth , Marcel Apfelbaum , Aleksandar Markovic , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Laurent Vivier , qemu-trivial@nongnu.org Subject: [PATCH 1/4] hw: Replace magic value by PCI_NUM_PINS definition Date: Sun, 11 Oct 2020 21:49:15 +0200 Message-Id: <20201011194918.3219195-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201011194918.3219195-1-f4bug@amsat.org> References: <20201011194918.3219195-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use self-explicit PCI_NUM_PINS definition instead of magic value. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/virt.c | 4 ++-- hw/mips/gt64xxx_pci.c | 2 +- hw/pci-host/versatile.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e465a988d68..ddad9621f79 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1117,11 +1117,11 @@ static void create_pcie_irq_map(const VirtMachineSt= ate *vms, int first_irq, const char *nodename) { int devfn, pin; - uint32_t full_irq_map[4 * 4 * 10] =3D { 0 }; + uint32_t full_irq_map[4 * PCI_NUM_PINS * 10] =3D { 0 }; uint32_t *irq_map =3D full_irq_map; =20 for (devfn =3D 0; devfn <=3D 0x18; devfn +=3D 0x8) { - for (pin =3D 0; pin < 4; pin++) { + for (pin =3D 0; pin < PCI_NUM_PINS; pin++) { int irq_type =3D GIC_FDT_IRQ_TYPE_SPI; int irq_nr =3D first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_= PINS); int irq_level =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index e091bc4ed55..ff1a35755f6 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -1018,7 +1018,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq= _num, int level) if (pic_irq < 16) { /* The pic level is the logical OR of all the PCI irqs mapped to i= t. */ pic_level =3D 0; - for (i =3D 0; i < 4; i++) { + for (i =3D 0; i < PCI_NUM_PINS; i++) { if (pic_irq =3D=3D piix4_dev->config[PIIX_PIRQCA + i]) { pic_level |=3D pci_irq_levels[i]; } diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 3553277f941..b4951023f4e 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -75,7 +75,7 @@ enum { struct PCIVPBState { PCIHostState parent_obj; =20 - qemu_irq irq[4]; + qemu_irq irq[PCI_NUM_PINS]; MemoryRegion controlregs; MemoryRegion mem_config; MemoryRegion mem_config2; @@ -412,7 +412,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **e= rrp) =20 object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_VERSATILE_PCI_= HOST); =20 - for (i =3D 0; i < 4; i++) { + for (i =3D 0; i < PCI_NUM_PINS; i++) { sysbus_init_irq(sbd, &s->irq[i]); } =20 @@ -422,7 +422,7 @@ static void pci_vpb_realize(DeviceState *dev, Error **e= rrp) mapfn =3D pci_vpb_map_irq; } =20 - pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, 4); + pci_bus_irqs(&s->pci_bus, pci_vpb_set_irq, mapfn, s->irq, PCI_NUM_PINS= ); =20 /* Our memory regions are: * 0 : our control registers --=20 2.26.2