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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id 205sm2705471wme.38.2020.10.10.13.43.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2020 13:43:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XRaXNqZj1/ZpqBQYjItAcS8COgAJ0fcoH+Bv4m/WMkU=; b=DfSXBCwFkm7AU7OIi7r40sbkp4c8IHjKeJz3mLwgCHcEg4QkLnvmP9w3p7ojnyc0IF uSLy2EnaZqFrfPO6NdT2TW2g/V3S5yCtaWUaEBMix6Q/LY+M0DmbYfZIMeA4m0sLImW4 bkYJ0afEBKuFcvcDq6wjY4zxxHbO+/7UPpLM5IuAAMJqridqqaEsoHFal5as0mU8fMl3 KXqOIqEBsOqyqzM7CJoID2PGLZ6PeJk6zFzGmMaljuKUiECRKJMX6D+JSBdaabG01jRS s9DxeTEW9mrWpiphdkcveHQbDNyqp14GsUvHrUlFAqExDzOJOvBDn4wJAkXxgsj6d0Aj +IDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=XRaXNqZj1/ZpqBQYjItAcS8COgAJ0fcoH+Bv4m/WMkU=; b=Hwn037IFaZ4gih2UeaNdN+0NvSmars7ze+Z70zhduA/c2lK8jKZeEkfrtvXNwCgAgi RzudsynWlCm9YQPCnOJbJij+s5Cv9n9go3tF1QOACXrC3wWSHQGFt0Ek93zmpjsyZjw/ Idf0NAoMaM84TDomeS/aOLCMbVDF7sNZ202FYrWev+xjyrJnD4HV0EbUK59QnIQmMTxI vW+susRcHgfM2VMcuVJaJMgIW6f/NopErM9IOGuLTROrxmneFCSItPvTiqcprCp78LF8 BBX5Q5kBd2iOQCrxP2Lj0zdmWbD5zc0EyrN8hTDnAal6KXWtV/F7Dnhm4/TZYi4Q+lNK Ai1A== X-Gm-Message-State: AOAM533SZlkKxRdraVjzbWJC1pK9OSkrp6YBWBJa9/K4TTkg3PnbZhwO zKBQg8Hkd9pBagX0fftgerY= X-Google-Smtp-Source: ABdhPJzOPmowwrrFrF0ni31Rg4i9HMU+72MjO99S0VhBrQd1mcONSnqTS/nJgkF5mveE/g1UOcrnkA== X-Received: by 2002:adf:f709:: with SMTP id r9mr21974258wrp.266.1602362626564; Sat, 10 Oct 2020 13:43:46 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Damien Hedde , Paul Burton , Luc Michel , Aleksandar Rikalo , Huacai Chen , Richard Henderson , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang Subject: [PATCH v3 18/20] hw/mips/malta: Set CPU frequency to 320 MHz Date: Sat, 10 Oct 2020 22:43:17 +0200 Message-Id: <20201010204319.3119239-19-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201010204319.3119239-1-f4bug@amsat.org> References: <20201010204319.3119239-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The CoreLV card with ID 0x420's CPU clocked at 320 MHz. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/malta.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 4019c9dc1a8..357e269e088 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -57,6 +57,7 @@ #include "sysemu/kvm.h" #include "hw/semihosting/semihost.h" #include "hw/mips/cps.h" +#include "hw/qdev-clock.h" =20 #define ENVP_ADDR 0x80002000l #define ENVP_NB_ENTRIES 16 @@ -94,6 +95,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA) struct MaltaState { SysBusDevice parent_obj; =20 + Clock *cpuclk; MIPSCPSState cps; qemu_irq i8259[ISA_NUM_IRQS]; }; @@ -1159,7 +1161,7 @@ static void main_cpu_reset(void *opaque) } } =20 -static void create_cpu_without_cps(MachineState *ms, +static void create_cpu_without_cps(MachineState *ms, MaltaState *s, qemu_irq *cbus_irq, qemu_irq *i8259_irq) { CPUMIPSState *env; @@ -1167,7 +1169,9 @@ static void create_cpu_without_cps(MachineState *ms, int i; =20 for (i =3D 0; i < ms->smp.cpus; i++) { - cpu =3D MIPS_CPU(cpu_create(ms->cpu_type)); + cpu =3D MIPS_CPU(object_new(ms->cpu_type)); + qdev_connect_clock_in(DEVICE(cpu), "clk-in", s->cpuclk); + qdev_realize(DEVICE(cpu), NULL, &error_abort); =20 /* Init internal devices */ cpu_mips_irq_init_cpu(cpu); @@ -1189,6 +1193,7 @@ static void create_cps(MachineState *ms, MaltaState *= s, &error_fatal); object_property_set_int(OBJECT(&s->cps), "num-vp", ms->smp.cpus, &error_fatal); + qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); =20 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); @@ -1203,7 +1208,7 @@ static void mips_create_cpu(MachineState *ms, MaltaSt= ate *s, if ((ms->smp.cpus > 1) && cpu_supports_cps_smp(ms->cpu_type)) { create_cps(ms, s, cbus_irq, i8259_irq); } else { - create_cpu_without_cps(ms, cbus_irq, i8259_irq); + create_cpu_without_cps(ms, s, cbus_irq, i8259_irq); } } =20 @@ -1421,10 +1426,19 @@ void mips_malta_init(MachineState *machine) pci_vga_init(pci_bus); } =20 +static void mips_malta_instance_init(Object *obj) +{ + MaltaState *s =3D MIPS_MALTA(obj); + + s->cpuclk =3D qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); + clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */ +} + static const TypeInfo mips_malta_device =3D { .name =3D TYPE_MIPS_MALTA, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(MaltaState), + .instance_init =3D mips_malta_instance_init, }; =20 static void mips_malta_machine_init(MachineClass *mc) --=20 2.26.2