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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id 205sm2705471wme.38.2020.10.10.13.43.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2020 13:43:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tuhwN9e0WSQZgRYxEuwcxUwJNzQu5uaCHtzj/pF8FV8=; b=WjJ2XBd45BHbf8V8fFK0yRD+Ovc/I5c4zgpdERaxf7X5QeTph026mFwxkVL3VrzvCw FOLCLhUdJIhoG5M4Iy5NC8dixv8CUynO3QA1ohzNN5jcU5QqcHhtQYBxmzV86m6WgRNY pjuD4OX22igKQCwt5IV9RBmuqngf2aV21b9MGxs3DVveSaELX/styCJRYc5vQ3qf9tj2 J+v168x1YwgElvpiFTYsYB/uovpNMtFlqKn86VRaphcRk9bsDGLL7WdIQLOu4CeERPWB 5bpzVW8djXwk2d2U+o4E+ZkJ04VPONP2yGYAT1nPUkqxyyWdooHj6I3061Fknq5cOBfw YxHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=tuhwN9e0WSQZgRYxEuwcxUwJNzQu5uaCHtzj/pF8FV8=; b=W5HX9+180X+wktAPR1he1ZyFb6NVRM2rvcuIfrSld9N2SEp0HdSZoYKsC7irf+V/NN ANepHjqFwhPFhvMcjY4i4eT5M2oLtkKMK32cP48zBb0zR9EHMWdL9dwYElpqYURVg5Hn /f534WTLI5G8g35Phk71NIacnt8+J92AtusUdxckC+nv3Uft2EiiEOhR8Bw7eojPphFv N/IXNr5yedKqFaUAqoLobxiKki+h7sDfr0TRrkrPuWwNeNdFG6vCCMpzV7K3KMDCVVim 5Z8GV74Vk1aB/YXo63b+uYoQulgeAGOx3BWCgPrNBeM5l0tU0amvYhzb7SgWsKz5gqs9 e87g== X-Gm-Message-State: AOAM5300TbMXTqYJ02mZBszxxUz9QHaZQ3OJM52bp5977hdlH6n7/ZwQ A1fKiQQhcYDqTWA/csHTNkU= X-Google-Smtp-Source: ABdhPJxrVq9BYmHw1gI17OCYsI8WGUc3ETd+6Y7Lwrv2+52kkadbhr22KtOjeVTZQ6Mqq4fQFTdU1g== X-Received: by 2002:a1c:dc43:: with SMTP id t64mr4116412wmg.6.1602362625098; Sat, 10 Oct 2020 13:43:45 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Damien Hedde , Paul Burton , Luc Michel , Aleksandar Rikalo , Huacai Chen , Richard Henderson , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= , Eduardo Habkost , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Paolo Bonzini , Aurelien Jarno , Jiaxun Yang Subject: [PATCH v3 17/20] hw/mips/boston: Set CPU frequency to 1 GHz Date: Sat, 10 Oct 2020 22:43:16 +0200 Message-Id: <20201010204319.3119239-18-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201010204319.3119239-1-f4bug@amsat.org> References: <20201010204319.3119239-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) The I6400 can run at 1 GHz or more. Create a 'cpuclk' output clock and connect it to the CPU input clock. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/boston.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 1b3f69e949c..cf2296f4488 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -30,6 +30,7 @@ #include "hw/mips/cps.h" #include "hw/mips/cpudevs.h" #include "hw/pci-host/xilinx-pcie.h" +#include "hw/qdev-clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" #include "qemu/error-report.h" @@ -54,6 +55,7 @@ struct BostonState { MachineState *mach; MIPSCPSState cps; SerialMM *uart; + Clock *cpuclk; =20 CharBackend lcd_display; char lcd_content[8]; @@ -251,10 +253,19 @@ static const MemoryRegionOps boston_platreg_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static void mips_boston_instance_init(Object *obj) +{ + BostonState *s =3D BOSTON(obj); + + s->cpuclk =3D qdev_init_clock_out(DEVICE(obj), "cpu-refclk"); + clock_set_hz(s->cpuclk, 1000000000); /* 1 GHz */ +} + static const TypeInfo boston_device =3D { .name =3D TYPE_MIPS_BOSTON, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(BostonState), + .instance_init =3D mips_boston_instance_init, }; =20 static void boston_register_types(void) @@ -462,6 +473,8 @@ static void boston_mach_init(MachineState *machine) &error_fatal); object_property_set_int(OBJECT(&s->cps), "num-vp", machine->smp.cpus, &error_fatal); + qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", + qdev_get_clock_out(dev, "cpu-refclk")); sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal); =20 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1); --=20 2.26.2