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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id i11sm16786068wre.32.2020.10.10.10.26.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2020 10:26:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GJs+vUPbnbBqVHsKvcVatNykiV7Rg7UUaqvKVc5FZic=; b=eYaWz2r4mRDquzy6uPEASAgNB9lW5MXM+p33nvjo4eNH4/HLgmqjrrU3eA1UNEGiG5 KYi/9fzBjRD6ZTrcB2wzxiLIfiPOQTb3/A8ljKXrgxvsbxMaEt6xW0lmj6+bvjnZohr7 fmYwmA6GRa96eVLv0Yv4ymyZhJInfjJRXiVehjc7hOiU6rkZI5xtHuUlHOa+Cb0w9CJ9 UOo1mB2z5V82SfMp4/9RmfIeOoXpawAswsdeQNKtU1cAx9OExam5QoJPuD4O+26kFpKV K3DjsboCL/H0ZDMVHa/H93p05RPi1Tqnjy+MyV8rlzaVUBTTu10HIXDU4C37MJNdftqN 0O5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GJs+vUPbnbBqVHsKvcVatNykiV7Rg7UUaqvKVc5FZic=; b=pfwVkTi33aIQKQhFx7D5FiYNmtDXO04HWRmHelPE5EDriqLK8PcNSxsUwYhfqicErM KrQ6lvMZFUy5iL8HLsFvkf1/ZU525GEsPaR2xHY/6BbiZdVc8iTQHDzYrf22GxE/wORG Z1zu3SODrtUciPp4617KqLEyPSOq+E1PvJ6DggeapOj2LDhwIHH4yS91Ar4lN7+LOqck Tm3Jp3XyFahjRm7lnT95EzSI+vvS8YxkoaLmAbX0fujcC0Vv9pk3sHNDGw23SZlbDja8 ALEaihSzQovcRgsmXXTru+vGyzv5BRWqw4ifzcsfrCQIcLXaB9TkdUe72QS7e3uXjKZj mSAQ== X-Gm-Message-State: AOAM530oV/ckAk0Q0Y6ShjUU4gvSYkMEa+Qv6mQz5pFdkItRF/eif4Ee LqFFvwEcs5PhO1XCEpvCM8o= X-Google-Smtp-Source: ABdhPJxempHW8LfOowFAaxwgAsUhj6DQ5ykFG16WIUxFlaJuzZFMZyRjPbUSCsyVE5txDc4nM/8e9A== X-Received: by 2002:a1c:a9d1:: with SMTP id s200mr3458266wme.107.1602350795548; Sat, 10 Oct 2020 10:26:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Huacai Chen , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Paul Burton , Jiaxun Yang , Luc Michel Subject: [PATCH v2 11/20] target/mips/cpu: Allow the CPU to use dynamic frequencies Date: Sat, 10 Oct 2020 19:26:08 +0200 Message-Id: <20201010172617.3079633-12-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201010172617.3079633-1-f4bug@amsat.org> References: <20201010172617.3079633-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Use the Clock API and let the CPU object have an input clock. If no clock is connected, keep using the default frequency of 200 MHz used since the introduction of the 'r4k' machine in commit 6af0bf9c7c3. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 4 ++++ target/mips/cpu.c | 10 ++++++++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index baeceb892ef..062a4ba6225 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -4,6 +4,7 @@ #include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" +#include "hw/clock.h" #include "mips-defs.h" =20 #define TCG_GUEST_DEFAULT_MO (0) @@ -1151,6 +1152,8 @@ struct CPUMIPSState { /** * MIPSCPU: * @env: #CPUMIPSState + * @clock: this CPU input clock (may be connected + * to an output clock from another device). * @cp0_count_rate: rate at which the coprocessor 0 counter increments * * A MIPS CPU. @@ -1160,6 +1163,7 @@ struct MIPSCPU { CPUState parent_obj; /*< public >*/ =20 + Clock *clock; CPUNegativeOffsetState neg; CPUMIPSState env; /* diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 461edfe22b7..3deb0245e7c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -27,6 +27,7 @@ #include "sysemu/kvm.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" +#include "hw/qdev-clock.h" =20 static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -144,8 +145,8 @@ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; =20 - env->cp0_count_ns =3D muldiv64(NANOSECONDS_PER_SECOND, cpu->cp0_count_= rate, - CPU_FREQ_HZ_DEFAULT); + env->cp0_count_ns =3D cpu->cp0_count_rate + * clock_get_ns(MIPS_CPU(cpu)->clock); } =20 static void mips_cpu_realizefn(DeviceState *dev, Error **errp) @@ -155,6 +156,10 @@ static void mips_cpu_realizefn(DeviceState *dev, Error= **errp) MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 + if (!clock_get(cpu->clock)) { + /* Initialize the frequency in case the clock remains unconnected.= */ + clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); + } mips_cp0_period_set(cpu); =20 cpu_exec_realizefn(cs, &local_err); @@ -178,6 +183,7 @@ static void mips_cpu_initfn(Object *obj) MIPSCPUClass *mcc =3D MIPS_CPU_GET_CLASS(obj); =20 cpu_set_cpustate_pointers(cpu); + cpu->clock =3D qdev_init_clock_in(DEVICE(obj), "clk-in", NULL, cpu); env->cpu_model =3D mcc->cpu_def; } =20 --=20 2.26.2