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[83.59.162.106]) by smtp.gmail.com with ESMTPSA id i11sm16786068wre.32.2020.10.10.10.26.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Oct 2020 10:26:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i1cGbjc5Cl94JMQEfZlvF0v5MlNUEPZb+r7dtqjcBUs=; b=SKKtqH7MaIjmjoZzCPXDhMH+IUc5IO5PRCMeH50ranrtbo6BJnubq9H2E2oyTpPaNT hOajyPLpYYN/WZhtEkNIKPwVmsFbiooWU76zV1b1l31SoSNsCi1ALQhfGn3LUaX6+LIC zoXr388r31tGNsdoLot1pv96jY7XoPWLqFO0E6yqKC8M3+W/GYPXLTpru3RwifLuQ/X+ om3FkmjeGzQ+k+0zQAR7Lg1ZOCugMM38x/XMQhjgHeOkifPY0gg5e6XfuDkfLFIjvset a+mIiun4Abr/RhP+hD6HekM+YjpdUS5ojhih4QYhtWdiP6pmqaEyhITTQ74IlPhPouUN ZMyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=i1cGbjc5Cl94JMQEfZlvF0v5MlNUEPZb+r7dtqjcBUs=; b=n1lXMPYcjArhFvsjD0KXZQta60Sr7d50oZMfSkW7RnOlSsUdGMyTPjJfgS13S2cr4d 7rn16PTDJYWw8NCX6UklocJgd7P+HPA7wVn5RprVXiefdfMX7WIz0j+Ybx+U1Vg2vtrl 08MTtqlXH4MDCrJPKj1EmGUwoRUlNyZJ9LFgJXd0wIswSiWWpfBN+sU08tAKEJe1HIK/ WqXui2PG/hAJuAiPylDK7yGBf4hlmu3YkHqclbioy3d8+QR61yZFtU7lhsJZzDSSOjrp OMXH4/7hx7cq3AXnYaXKJ5RYL2JXKilamoMNwDLShGi0ncR0+sGYWP6FTP7i75riNdG8 k6cA== X-Gm-Message-State: AOAM533j8adMst2+0ij4pzJpbPpAERMt7tsHhvnnKFTFTySnx72yrL1U oFGgR//HmWD5sXiqpela+v0= X-Google-Smtp-Source: ABdhPJzAbaZ6zR9VIiJSLmay4Mk9SWsp+Y/6KB/Vzfw+vEooVmyzOYESI8DDN0ySMYrtB2zV3H3ulA== X-Received: by 2002:a5d:63c3:: with SMTP id c3mr20630624wrw.315.1602350794356; Sat, 10 Oct 2020 10:26:34 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Damien Hedde , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Huacai Chen , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , Paolo Bonzini , Aurelien Jarno , Huacai Chen , Aleksandar Rikalo , Paul Burton , Jiaxun Yang , Luc Michel Subject: [PATCH v2 10/20] target/mips/cpu: Make cp0_count_rate a property Date: Sat, 10 Oct 2020 19:26:07 +0200 Message-Id: <20201010172617.3079633-11-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20201010172617.3079633-1-f4bug@amsat.org> References: <20201010172617.3079633-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Since not all CPU implementations use a cores use a CP0 timer at half the frequency of the CPU, make this variable a property. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/cpu.h | 9 +++++++++ target/mips/cpu.c | 19 +++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 085a88e9550..baeceb892ef 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1151,6 +1151,7 @@ struct CPUMIPSState { /** * MIPSCPU: * @env: #CPUMIPSState + * @cp0_count_rate: rate at which the coprocessor 0 counter increments * * A MIPS CPU. */ @@ -1161,6 +1162,14 @@ struct MIPSCPU { =20 CPUNegativeOffsetState neg; CPUMIPSState env; + /* + * The Count register acts as a timer, incrementing at a constant rate, + * whether or not an instruction is executed, retired, or any forward + * progress is made through the pipeline. The rate at which the counter + * increments is implementation dependent, and is a function of the + * pipeline clock of the processor, not the issue width of the process= or. + */ + unsigned cp0_count_rate; }; =20 =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 46188139b7b..461edfe22b7 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -26,7 +26,7 @@ #include "qemu/module.h" #include "sysemu/kvm.h" #include "exec/exec-all.h" - +#include "hw/qdev-properties.h" =20 static void mips_cpu_set_pc(CPUState *cs, vaddr value) { @@ -135,12 +135,7 @@ static void mips_cpu_disas_set_info(CPUState *s, disas= semble_info *info) } =20 /* - * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz - * and a CP0 timer running at half the clock of the CPU (cp0_count_rate = =3D 2). - * - * TIMER_FREQ_HZ =3D CPU_FREQ_HZ / CP0_COUNT_RATE =3D 200 MHz / 2 =3D 100 = MHz - * - * TIMER_PERIOD_NS =3D 1 / TIMER_FREQ_HZ =3D 10 ns + * Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz. */ #define CPU_FREQ_HZ_DEFAULT 200000000 #define CP0_COUNT_RATE_DEFAULT 2 @@ -149,7 +144,7 @@ static void mips_cp0_period_set(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; =20 - env->cp0_count_ns =3D muldiv64(NANOSECONDS_PER_SECOND, CP0_COUNT_RATE_= DEFAULT, + env->cp0_count_ns =3D muldiv64(NANOSECONDS_PER_SECOND, cpu->cp0_count_= rate, CPU_FREQ_HZ_DEFAULT); } =20 @@ -202,6 +197,13 @@ static ObjectClass *mips_cpu_class_by_name(const char = *cpu_model) return oc; } =20 +static Property mips_cpu_properties[] =3D { + /* CP0 timer running at half the clock of the CPU */ + DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate, + CP0_COUNT_RATE_DEFAULT), + DEFINE_PROP_END_OF_LIST() +}; + static void mips_cpu_class_init(ObjectClass *c, void *data) { MIPSCPUClass *mcc =3D MIPS_CPU_CLASS(c); @@ -211,6 +213,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); + device_class_set_props(dc, mips_cpu_properties); =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; --=20 2.26.2