From nobody Tue Feb 10 05:46:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602338688937841.3948697404038; Sat, 10 Oct 2020 07:04:48 -0700 (PDT) Received: from localhost ([::1]:42486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kRFUN-0002ro-Jt for importer@patchew.org; Sat, 10 Oct 2020 10:04:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kRFN4-00018H-Bi; Sat, 10 Oct 2020 09:57:14 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:43614) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kRFN0-0004Jz-Io; Sat, 10 Oct 2020 09:57:13 -0400 Received: from sekoia-pc.home.lmichel.fr (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id 5C6A7C603DA; Sat, 10 Oct 2020 13:57:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1602338224; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NmpeIs/KxZ0nwoVwshfm33d4zNSTn7PVf5VKmIRAe2o=; b=EMhBCi/CuWvYgCyPn22FYgxncqcQrw84UAlEPg0AXQw53RWyv+XRCznI63l1GBydH4T9Qt p4qNQr0DZda8JvKKPD4QgnZYlU8BYEQSlElV5QmRp6/XpTTpqD4qLi8ETWLvblV9UWYD/p ZNZa7sZl3Bla9HnXa+DtNvQOIQSHlSNqAKxJCpljdBdPKSnLRpiitglu8J8NroYOkTK2nv V7J2h0tlqbcCt2pBRkVyKor6fUS4DBG+Yjval0dvOG5VzDNoOzQt3WJXth48GN5vTXONmz A6J/NQhWmiomIeWFdJ4Q7bqhiphFRi/8v5NpaUMH+yAAVBJlndGzvoQ5mJaeDg== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH v3 08/15] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation Date: Sat, 10 Oct 2020 15:57:52 +0200 Message-Id: <20201010135759.437903-9-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20201010135759.437903-1-luc@lmichel.fr> References: <20201010135759.437903-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1602338224; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NmpeIs/KxZ0nwoVwshfm33d4zNSTn7PVf5VKmIRAe2o=; b=EDtId9VqGPn4xpe45flHbU49IMwWqYx3XCb5qHFBwZrY6ZPQy83Z2y4Zw3Tk90QkI8d2NY dRfR5sEda3rEdeqPk1ul7VENokaLJEd7kxKoQSzP8WRcpESuTrmHTs6Iq/AaDyoyI5eRlV T6EEOEvQYx+MeDSuYWp0b7nwU0O6Y9xum7ALMXWRFIJ0TiF0EUbYdIEHL8+/O/uh527/DN QAhNGTbHUY+Et3nRiND5ApJ5305n+rxDnD3USfmTUMq6I+zj0s/OPIFpSC+8gZ4eC4u0TG G4hoLnBxiDo0LMeDFAUynCV8QzpsFclmfAFiFQczNy/EJnAXjS4/yYYfOozDUA== ARC-Seal: i=1; s=pharaoh; d=lmichel.fr; t=1602338224; a=rsa-sha256; cv=none; b=ZlWTM9fYUIlCw79trw1bQiKTrscUJHTOhZ7THPY6GBL4STP/Sbj8hjCwV+ST6oIiTpb+/UUCQO0wYKtWAIYisUW+LmkJCzht2nqtOoGOvc2Qun9MFqmyMrw060Eq/lx+JgsvZcEHdqGFzWkaT126RTNB0eL37CyHL+WQyMgsutymEoIkqtaC6/Er0ZrYMsMSSlft4YjK1JZbRjOJaJmyrN5TlLK5kOWbIxdS8P4IGri1gK0hJHx455YeEvT/WGZXjtdQyr/k7N5MBTYcELc1VZ7a9VpMoKAEPtX0eCb6WJZ44QOyV8S3d4PemtD9GYJDO0w2nICtk4NUT9XONlwMHA== ARC-Authentication-Results: i=1; pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/10 07:32:09 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Paul Zimmerman , Niek Linnenbank , qemu-arm@nongnu.org, Havard Skinnemoen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) PLLs are composed of multiple channels. Each channel outputs one clock signal. They are modeled as one device taking the PLL generated clock as input, and outputting a new clock. A channel shares the CM register with its parent PLL, and has its own A2W_CTRL register. A write to the CM register will trigger an update of the PLL and all its channels, while a write to an A2W_CTRL channel register will update the required channel only. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Luc Michel --- include/hw/misc/bcm2835_cprman.h | 44 ++++++ include/hw/misc/bcm2835_cprman_internals.h | 146 +++++++++++++++++++ hw/misc/bcm2835_cprman.c | 155 +++++++++++++++++++-- 3 files changed, 337 insertions(+), 8 deletions(-) diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr= man.h index 5c442e6ff9..e1a1b33f8b 100644 --- a/include/hw/misc/bcm2835_cprman.h +++ b/include/hw/misc/bcm2835_cprman.h @@ -29,10 +29,35 @@ typedef enum CprmanPll { CPRMAN_PLLB, =20 CPRMAN_NUM_PLL } CprmanPll; =20 +typedef enum CprmanPllChannel { + CPRMAN_PLLA_CHANNEL_DSI0 =3D 0, + CPRMAN_PLLA_CHANNEL_CORE, + CPRMAN_PLLA_CHANNEL_PER, + CPRMAN_PLLA_CHANNEL_CCP2, + + CPRMAN_PLLC_CHANNEL_CORE2, + CPRMAN_PLLC_CHANNEL_CORE1, + CPRMAN_PLLC_CHANNEL_PER, + CPRMAN_PLLC_CHANNEL_CORE0, + + CPRMAN_PLLD_CHANNEL_DSI0, + CPRMAN_PLLD_CHANNEL_CORE, + CPRMAN_PLLD_CHANNEL_PER, + CPRMAN_PLLD_CHANNEL_DSI1, + + CPRMAN_PLLH_CHANNEL_AUX, + CPRMAN_PLLH_CHANNEL_RCAL, + CPRMAN_PLLH_CHANNEL_PIX, + + CPRMAN_PLLB_CHANNEL_ARM, + + CPRMAN_NUM_PLL_CHANNEL, +} CprmanPllChannel; + typedef struct CprmanPllState { /*< private >*/ DeviceState parent_obj; =20 /*< public >*/ @@ -46,18 +71,37 @@ typedef struct CprmanPllState { =20 Clock *xosc_in; Clock *out; } CprmanPllState; =20 +typedef struct CprmanPllChannelState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CprmanPllChannel id; + CprmanPll parent; + + uint32_t *reg_cm; + uint32_t hold_mask; + uint32_t load_mask; + uint32_t *reg_a2w_ctrl; + int fixed_divider; + + Clock *pll_in; + Clock *out; +} CprmanPllChannelState; + struct BCM2835CprmanState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; =20 CprmanPllState plls[CPRMAN_NUM_PLL]; + CprmanPllChannelState channels[CPRMAN_NUM_PLL_CHANNEL]; =20 uint32_t regs[CPRMAN_NUM_REGS]; uint32_t xosc_freq; =20 Clock *xosc; diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index 7aa46c6e18..7409ddb024 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -11,13 +11,16 @@ =20 #include "hw/registerfields.h" #include "hw/misc/bcm2835_cprman.h" =20 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll" +#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel" =20 DECLARE_INSTANCE_CHECKER(CprmanPllState, CPRMAN_PLL, TYPE_CPRMAN_PLL) +DECLARE_INSTANCE_CHECKER(CprmanPllChannelState, CPRMAN_PLL_CHANNEL, + TYPE_CPRMAN_PLL_CHANNEL) =20 /* Register map */ =20 /* PLLs */ REG32(CM_PLLA, 0x104) @@ -98,10 +101,35 @@ REG32(A2W_PLLA_FRAC, 0x1200) REG32(A2W_PLLC_FRAC, 0x1220) REG32(A2W_PLLD_FRAC, 0x1240) REG32(A2W_PLLH_FRAC, 0x1260) REG32(A2W_PLLB_FRAC, 0x12e0) =20 +/* PLL channels */ +REG32(A2W_PLLA_DSI0, 0x1300) + FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8) + FIELD(A2W_PLLx_CHANNELy, DISABLE, 8, 1) +REG32(A2W_PLLA_CORE, 0x1400) +REG32(A2W_PLLA_PER, 0x1500) +REG32(A2W_PLLA_CCP2, 0x1600) + +REG32(A2W_PLLC_CORE2, 0x1320) +REG32(A2W_PLLC_CORE1, 0x1420) +REG32(A2W_PLLC_PER, 0x1520) +REG32(A2W_PLLC_CORE0, 0x1620) + +REG32(A2W_PLLD_DSI0, 0x1340) +REG32(A2W_PLLD_CORE, 0x1440) +REG32(A2W_PLLD_PER, 0x1540) +REG32(A2W_PLLD_DSI1, 0x1640) + +REG32(A2W_PLLH_AUX, 0x1360) +REG32(A2W_PLLH_RCAL, 0x1460) +REG32(A2W_PLLH_PIX, 0x1560) +REG32(A2W_PLLH_STS, 0x1660) + +REG32(A2W_PLLB_ARM, 0x13e0) + /* misc registers */ REG32(CM_LOCK, 0x114) FIELD(CM_LOCK, FLOCKH, 12, 1) FIELD(CM_LOCK, FLOCKD, 11, 1) FIELD(CM_LOCK, FLOCKC, 10, 1) @@ -171,6 +199,124 @@ static inline void set_pll_init_info(BCM2835CprmanSta= te *s, pll->reg_a2w_ana =3D &s->regs[PLL_INIT_INFO[id].a2w_ana_offset]; pll->prediv_mask =3D PLL_INIT_INFO[id].prediv_mask; pll->reg_a2w_frac =3D &s->regs[PLL_INIT_INFO[id].a2w_frac_offset]; } =20 + +/* PLL channel init info */ +typedef struct PLLChannelInitInfo { + const char *name; + CprmanPll parent; + size_t cm_offset; + uint32_t cm_hold_mask; + uint32_t cm_load_mask; + size_t a2w_ctrl_offset; + unsigned int fixed_divider; +} PLLChannelInitInfo; + +#define FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_) \ + .parent =3D CPRMAN_ ## pll_, \ + .cm_offset =3D R_CM_ ## pll_, \ + .cm_load_mask =3D R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \ + .a2w_ctrl_offset =3D R_A2W_ ## pll_ ## _ ## channel_ + +#define FILL_PLL_CHANNEL_INIT_INFO(pll_, channel_) \ + FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \ + .cm_hold_mask =3D R_CM_ ## pll_ ## _ ## HOLD ## channel_ ## _MASK, \ + .fixed_divider =3D 1 + +#define FILL_PLL_CHANNEL_INIT_INFO_nohold(pll_, channel_) \ + FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \ + .cm_hold_mask =3D 0 + +static PLLChannelInitInfo PLL_CHANNEL_INIT_INFO[] =3D { + [CPRMAN_PLLA_CHANNEL_DSI0] =3D { + .name =3D "plla-dsi0", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0), + }, + [CPRMAN_PLLA_CHANNEL_CORE] =3D { + .name =3D "plla-core", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, CORE), + }, + [CPRMAN_PLLA_CHANNEL_PER] =3D { + .name =3D "plla-per", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, PER), + }, + [CPRMAN_PLLA_CHANNEL_CCP2] =3D { + .name =3D "plla-ccp2", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, CCP2), + }, + + [CPRMAN_PLLC_CHANNEL_CORE2] =3D { + .name =3D "pllc-core2", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE2), + }, + [CPRMAN_PLLC_CHANNEL_CORE1] =3D { + .name =3D "pllc-core1", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE1), + }, + [CPRMAN_PLLC_CHANNEL_PER] =3D { + .name =3D "pllc-per", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, PER), + }, + [CPRMAN_PLLC_CHANNEL_CORE0] =3D { + .name =3D "pllc-core0", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE0), + }, + + [CPRMAN_PLLD_CHANNEL_DSI0] =3D { + .name =3D "plld-dsi0", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0), + }, + [CPRMAN_PLLD_CHANNEL_CORE] =3D { + .name =3D "plld-core", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, CORE), + }, + [CPRMAN_PLLD_CHANNEL_PER] =3D { + .name =3D "plld-per", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, PER), + }, + [CPRMAN_PLLD_CHANNEL_DSI1] =3D { + .name =3D "plld-dsi1", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI1), + }, + + [CPRMAN_PLLH_CHANNEL_AUX] =3D { + .name =3D "pllh-aux", + .fixed_divider =3D 1, + FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, AUX), + }, + [CPRMAN_PLLH_CHANNEL_RCAL] =3D { + .name =3D "pllh-rcal", + .fixed_divider =3D 10, + FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, RCAL), + }, + [CPRMAN_PLLH_CHANNEL_PIX] =3D { + .name =3D "pllh-pix", + .fixed_divider =3D 10, + FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, PIX), + }, + + [CPRMAN_PLLB_CHANNEL_ARM] =3D { + .name =3D "pllb-arm", + FILL_PLL_CHANNEL_INIT_INFO(PLLB, ARM), + }, +}; + +#undef FILL_PLL_CHANNEL_INIT_INFO_nohold +#undef FILL_PLL_CHANNEL_INIT_INFO +#undef FILL_PLL_CHANNEL_INIT_INFO_common + +static inline void set_pll_channel_init_info(BCM2835CprmanState *s, + CprmanPllChannelState *channe= l, + CprmanPllChannel id) +{ + channel->id =3D id; + channel->parent =3D PLL_CHANNEL_INIT_INFO[id].parent; + channel->reg_cm =3D &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset]; + channel->hold_mask =3D PLL_CHANNEL_INIT_INFO[id].cm_hold_mask; + channel->load_mask =3D PLL_CHANNEL_INIT_INFO[id].cm_load_mask; + channel->reg_a2w_ctrl =3D &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_= offset]; + channel->fixed_divider =3D PLL_CHANNEL_INIT_INFO[id].fixed_divider; +} + #endif diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 144bcc289d..12fa78181b 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -130,10 +130,73 @@ static const TypeInfo cprman_pll_info =3D { .class_init =3D pll_class_init, .instance_init =3D pll_init, }; =20 =20 +/* PLL channel */ + +static void pll_channel_update(CprmanPllChannelState *channel) +{ + clock_update(channel->out, 0); +} + +/* Update a PLL and all its channels */ +static void pll_update_all_channels(BCM2835CprmanState *s, + CprmanPllState *pll) +{ + size_t i; + + pll_update(pll); + + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + CprmanPllChannelState *channel =3D &s->channels[i]; + if (channel->parent =3D=3D pll->id) { + pll_channel_update(channel); + } + } +} + +static void pll_channel_pll_in_update(void *opaque) +{ + pll_channel_update(CPRMAN_PLL_CHANNEL(opaque)); +} + +static void pll_channel_init(Object *obj) +{ + CprmanPllChannelState *s =3D CPRMAN_PLL_CHANNEL(obj); + + s->pll_in =3D qdev_init_clock_in(DEVICE(s), "pll-in", + pll_channel_pll_in_update, s); + s->out =3D qdev_init_clock_out(DEVICE(s), "out"); +} + +static const VMStateDescription pll_channel_vmstate =3D { + .name =3D TYPE_CPRMAN_PLL_CHANNEL, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(pll_in, CprmanPllChannelState), + VMSTATE_END_OF_LIST() + } +}; + +static void pll_channel_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &pll_channel_vmstate; +} + +static const TypeInfo cprman_pll_channel_info =3D { + .name =3D TYPE_CPRMAN_PLL_CHANNEL, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CprmanPllChannelState), + .class_init =3D pll_channel_class_init, + .instance_init =3D pll_channel_init, +}; + + /* CPRMAN "top level" model */ =20 static uint32_t get_cm_lock(const BCM2835CprmanState *s) { static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] =3D { @@ -172,12 +235,36 @@ static uint64_t cprman_read(void *opaque, hwaddr offs= et, =20 trace_bcm2835_cprman_read(offset, r); return r; } =20 -#define CASE_PLL_REGS(pll_) \ - case R_CM_ ## pll_: \ +static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s, + size_t idx) +{ + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + if (PLL_INIT_INFO[i].cm_offset =3D=3D idx) { + pll_update_all_channels(s, &s->plls[i]); + return; + } + } +} + +static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t i= dx) +{ + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset =3D=3D idx) { + pll_channel_update(&s->channels[i]); + return; + } + } +} + +#define CASE_PLL_A2W_REGS(pll_) \ case R_A2W_ ## pll_ ## _CTRL: \ case R_A2W_ ## pll_ ## _ANA0: \ case R_A2W_ ## pll_ ## _ANA1: \ case R_A2W_ ## pll_ ## _ANA2: \ case R_A2W_ ## pll_ ## _ANA3: \ @@ -198,33 +285,61 @@ static void cprman_write(void *opaque, hwaddr offset, =20 trace_bcm2835_cprman_write(offset, value); s->regs[idx] =3D value; =20 switch (idx) { - CASE_PLL_REGS(PLLA) : + case R_CM_PLLA ... R_CM_PLLH: + case R_CM_PLLB: + /* + * A given CM_PLLx register is shared by both the PLL and the chan= nels + * of this PLL. + */ + update_pll_and_channels_from_cm(s, idx); + break; + + CASE_PLL_A2W_REGS(PLLA) : pll_update(&s->plls[CPRMAN_PLLA]); break; =20 - CASE_PLL_REGS(PLLC) : + CASE_PLL_A2W_REGS(PLLC) : pll_update(&s->plls[CPRMAN_PLLC]); break; =20 - CASE_PLL_REGS(PLLD) : + CASE_PLL_A2W_REGS(PLLD) : pll_update(&s->plls[CPRMAN_PLLD]); break; =20 - CASE_PLL_REGS(PLLH) : + CASE_PLL_A2W_REGS(PLLH) : pll_update(&s->plls[CPRMAN_PLLH]); break; =20 - CASE_PLL_REGS(PLLB) : + CASE_PLL_A2W_REGS(PLLB) : pll_update(&s->plls[CPRMAN_PLLB]); break; + + case R_A2W_PLLA_DSI0: + case R_A2W_PLLA_CORE: + case R_A2W_PLLA_PER: + case R_A2W_PLLA_CCP2: + case R_A2W_PLLC_CORE2: + case R_A2W_PLLC_CORE1: + case R_A2W_PLLC_PER: + case R_A2W_PLLC_CORE0: + case R_A2W_PLLD_DSI0: + case R_A2W_PLLD_CORE: + case R_A2W_PLLD_PER: + case R_A2W_PLLD_DSI1: + case R_A2W_PLLH_AUX: + case R_A2W_PLLH_RCAL: + case R_A2W_PLLH_PIX: + case R_A2W_PLLB_ARM: + update_channel_from_a2w(s, idx); + break; } } =20 -#undef CASE_PLL_REGS +#undef CASE_PLL_A2W_REGS =20 static const MemoryRegionOps cprman_ops =3D { .read =3D cprman_read, .write =3D cprman_write, .endianness =3D DEVICE_LITTLE_ENDIAN, @@ -252,10 +367,14 @@ static void cprman_reset(DeviceState *dev) =20 for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { device_cold_reset(DEVICE(&s->plls[i])); } =20 + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + device_cold_reset(DEVICE(&s->channels[i])); + } + clock_update_hz(s->xosc, s->xosc_freq); } =20 static void cprman_init(Object *obj) { @@ -266,10 +385,17 @@ static void cprman_init(Object *obj) object_initialize_child(obj, PLL_INIT_INFO[i].name, &s->plls[i], TYPE_CPRMAN_PLL); set_pll_init_info(s, &s->plls[i], i); } =20 + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name, + &s->channels[i], + TYPE_CPRMAN_PLL_CHANNEL); + set_pll_channel_init_info(s, &s->channels[i], i); + } + s->xosc =3D clock_new(obj, "xosc"); =20 memory_region_init_io(&s->iomem, obj, &cprman_ops, s, "bcm2835-cprman", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); @@ -287,10 +413,22 @@ static void cprman_realize(DeviceState *dev, Error **= errp) =20 if (!qdev_realize(DEVICE(pll), NULL, errp)) { return; } } + + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + CprmanPllChannelState *channel =3D &s->channels[i]; + CprmanPll parent =3D PLL_CHANNEL_INIT_INFO[i].parent; + Clock *parent_clk =3D s->plls[parent].out; + + clock_set_source(channel->pll_in, parent_clk); + + if (!qdev_realize(DEVICE(channel), NULL, errp)) { + return; + } + } } =20 static const VMStateDescription cprman_vmstate =3D { .name =3D TYPE_BCM2835_CPRMAN, .version_id =3D 1, @@ -326,8 +464,9 @@ static const TypeInfo cprman_info =3D { =20 static void cprman_register_types(void) { type_register_static(&cprman_info); type_register_static(&cprman_pll_info); + type_register_static(&cprman_pll_channel_info); } =20 type_init(cprman_register_types); --=20 2.28.0