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pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/10 07:32:09 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Paul Zimmerman , Niek Linnenbank , qemu-arm@nongnu.org, Havard Skinnemoen Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The CPRMAN PLLs generate a clock based on a prescaler, a multiplier and a divider. The prescaler doubles the parent (xosc) frequency, then the multiplier/divider are applied. The multiplier has an integer and a fractional part. This commit also implements the CPRMAN CM_LOCK register. This register reports which PLL is currently locked. We consider a PLL has being locked as soon as it is enabled (on real hardware, there is a delay after turning a PLL on, for it to stabilize). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Luc Michel --- include/hw/misc/bcm2835_cprman_internals.h | 8 +++ hw/misc/bcm2835_cprman.c | 64 +++++++++++++++++++++- 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index 340ad623bb..7aa46c6e18 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -98,10 +98,18 @@ REG32(A2W_PLLA_FRAC, 0x1200) REG32(A2W_PLLC_FRAC, 0x1220) REG32(A2W_PLLD_FRAC, 0x1240) REG32(A2W_PLLH_FRAC, 0x1260) REG32(A2W_PLLB_FRAC, 0x12e0) =20 +/* misc registers */ +REG32(CM_LOCK, 0x114) + FIELD(CM_LOCK, FLOCKH, 12, 1) + FIELD(CM_LOCK, FLOCKD, 11, 1) + FIELD(CM_LOCK, FLOCKC, 10, 1) + FIELD(CM_LOCK, FLOCKB, 9, 1) + FIELD(CM_LOCK, FLOCKA, 8, 1) + /* * This field is common to all registers. Each register write value must m= atch * the CPRMAN_PASSWORD magic value in its 8 MSB. */ FIELD(CPRMAN, PASSWORD, 24, 8) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index b86f5901b8..144bcc289d 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -48,13 +48,51 @@ #include "hw/misc/bcm2835_cprman_internals.h" #include "trace.h" =20 /* PLL */ =20 +static bool pll_is_locked(const CprmanPllState *pll) +{ + return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) + && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); +} + static void pll_update(CprmanPllState *pll) { - clock_update(pll->out, 0); + uint64_t freq, ndiv, fdiv, pdiv; + + if (!pll_is_locked(pll)) { + clock_update(pll->out, 0); + return; + } + + pdiv =3D FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); + + if (!pdiv) { + clock_update(pll->out, 0); + return; + } + + ndiv =3D FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); + fdiv =3D FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); + + if (pll->reg_a2w_ana[1] & pll->prediv_mask) { + /* The prescaler doubles the parent frequency */ + ndiv *=3D 2; + fdiv *=3D 2; + } + + /* + * We have a multiplier with an integer part (ndiv) and a fractional p= art + * (fdiv), and a divider (pdiv). + */ + freq =3D clock_get_hz(pll->xosc_in) * + ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv); + freq /=3D pdiv; + freq >>=3D R_A2W_PLLx_FRAC_FRAC_LENGTH; + + clock_update_hz(pll->out, freq); } =20 static void pll_xosc_update(void *opaque) { pll_update(CPRMAN_PLL(opaque)); @@ -94,18 +132,42 @@ static const TypeInfo cprman_pll_info =3D { }; =20 =20 /* CPRMAN "top level" model */ =20 +static uint32_t get_cm_lock(const BCM2835CprmanState *s) +{ + static const int CM_LOCK_MAPPING[CPRMAN_NUM_PLL] =3D { + [CPRMAN_PLLA] =3D R_CM_LOCK_FLOCKA_SHIFT, + [CPRMAN_PLLC] =3D R_CM_LOCK_FLOCKC_SHIFT, + [CPRMAN_PLLD] =3D R_CM_LOCK_FLOCKD_SHIFT, + [CPRMAN_PLLH] =3D R_CM_LOCK_FLOCKH_SHIFT, + [CPRMAN_PLLB] =3D R_CM_LOCK_FLOCKB_SHIFT, + }; + + uint32_t r =3D 0; + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + r |=3D pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; + } + + return r; +} + static uint64_t cprman_read(void *opaque, hwaddr offset, unsigned size) { BCM2835CprmanState *s =3D CPRMAN(opaque); uint64_t r =3D 0; size_t idx =3D offset / sizeof(uint32_t); =20 switch (idx) { + case R_CM_LOCK: + r =3D get_cm_lock(s); + break; + default: r =3D s->regs[idx]; } =20 trace_bcm2835_cprman_read(offset, r); --=20 2.28.0