From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602226759; cv=none; d=zohomail.com; s=zohoarc; b=WppTtZIxXWJoJCAaocEfD0W4hHwrPRZRZYjo8kwlovL15ATZbdj0vVL94hVZlodotJpJXdZ+9cwjpCiIAVlBdylETCu7sg3C0uU0ier5BpD8LLad2+5IZWPrk16kLwLiYN0/RIgUChFWHXvCndJHngjy8jRPONsfkhbxJkmVChI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602226759; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WqXSU8uImmSSpNURbv4h9FR3CyHw/8SEEMIcLOTG5Xo=; b=Q3ict20KQKFqctdFeQMfmAphsy+hDuUuhDFScKX/HRm5dwXY88u9XawQphRkLsH7Acm0bBlPO7oFIEb7Uuh6sTv6FYh+vi0duoQ/ZylucvKWvQSRV5gZApeEuj+41bNkLMMd7bwlj7nNgEAqqUfcTlpUdTfkLGiDkfVXrUDLXvs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602226759034901.9374255644606; Thu, 8 Oct 2020 23:59:19 -0700 (PDT) Received: from localhost ([::1]:51602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmN3-00041m-Nx for importer@patchew.org; Fri, 09 Oct 2020 02:59:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56194) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmA4-0005nM-SF; Fri, 09 Oct 2020 02:45:54 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4774 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmA1-0001C5-2f; Fri, 09 Oct 2020 02:45:52 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 823846AE669EF6E15121; Fri, 9 Oct 2020 14:45:42 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:36 +0800 From: zhaolichang To: Subject: [PATCH V2 01/14] cris/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:36 +0800 Message-ID: <20201009064449.2336-2-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= cris. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson --- target/cris/helper.c | 6 +++--- target/cris/op_helper.c | 2 +- target/cris/translate.c | 14 +++++++------- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/target/cris/helper.c b/target/cris/helper.c index b5159b8357..50419e72c5 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -141,7 +141,7 @@ void crisv10_cpu_do_interrupt(CPUState *cs) assert(!(env->pregs[PR_CCS] & PFIX_FLAG)); switch (cs->exception_index) { case EXCP_BREAK: - /* These exceptions are genereated by the core itself. + /* These exceptions are generated by the core itself. ERP should point to the insn following the brk. */ ex_vec =3D env->trap_vector; env->pregs[PRV10_BRP] =3D env->pc; @@ -197,7 +197,7 @@ void cris_cpu_do_interrupt(CPUState *cs) =20 switch (cs->exception_index) { case EXCP_BREAK: - /* These exceptions are genereated by the core itself. + /* These exceptions are generated by the core itself. ERP should point to the insn following the brk. */ ex_vec =3D env->trap_vector; env->pregs[PR_ERP] =3D env->pc; @@ -256,7 +256,7 @@ void cris_cpu_do_interrupt(CPUState *cs) undefined. */ env->pc =3D cpu_ldl_code(env, env->pregs[PR_EBP] + ex_vec * 4); =20 - /* Clear the excption_index to avoid spurios hw_aborts for recursive + /* Clear the excption_index to avoid spurious hw_aborts for recursive bus faults. */ cs->exception_index =3D -1; =20 diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 6b1e7ae4a8..3c4aacc26a 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -231,7 +231,7 @@ static inline uint32_t evaluate_flags_writeback(CPUCRIS= State *env, { unsigned int x, z, mask; =20 - /* Extended arithmetics, leave the z flag alone. */ + /* Extended arithmetic, leave the z flag alone. */ x =3D env->cc_x; mask =3D env->cc_mask | X_FLAG; if (x) { diff --git a/target/cris/translate.c b/target/cris/translate.c index c312e6f8a6..16b0ef8073 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -348,7 +348,7 @@ static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TC= Gv ccs) tcg_temp_free(t); } =20 -/* Extended arithmetics on CRIS. */ +/* Extended arithmetic on CRIS. */ static inline void t_gen_add_flag(TCGv d, int flag) { TCGv c; @@ -725,7 +725,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, switch (op) { case CC_OP_ADD: tcg_gen_add_tl(dst, a, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_addx_carry(dc, dst); break; case CC_OP_ADDC: @@ -738,7 +738,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, break; case CC_OP_SUB: tcg_gen_sub_tl(dst, a, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_subx_carry(dc, dst); break; case CC_OP_MOVE: @@ -764,7 +764,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, break; case CC_OP_NEG: tcg_gen_neg_tl(dst, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_subx_carry(dc, dst); break; case CC_OP_LZ: @@ -787,7 +787,7 @@ static void cris_alu_op_exec(DisasContext *dc, int op, break; case CC_OP_CMP: tcg_gen_sub_tl(dst, a, b); - /* Extended arithmetics. */ + /* Extended arithmetic. */ t_gen_subx_carry(dc, dst); break; default: @@ -3053,12 +3053,12 @@ static unsigned int crisv32_decoder(CPUCRISState *e= nv, DisasContext *dc) * On QEMU care needs to be taken when a branch+delayslot sequence is brok= en * and the branch and delayslot don't share pages. * - * The TB contaning the branch insn will set up env->btarget and evaluate=20 + * The TB containing the branch insn will set up env->btarget and evaluate=20 * env->btaken. When the translation loop exits we will note that the bran= ch=20 * sequence is broken and let env->dslot be the size of the branch insn (t= hose * vary in length). * - * The TB contaning the delayslot will have the PC of its real insn (i.e n= o lsb + * The TB containing the delayslot will have the PC of its real insn (i.e = no lsb * set). It will also expect to have env->dslot setup with the size of the=20 * delay slot so that env->pc - env->dslot point to the branch insn. This = TB=20 * will execute the dslot and take the branch, either to btarget or just o= ne=20 --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602226912; cv=none; d=zohomail.com; s=zohoarc; b=DDWGJoNPjtkaKi0fxrW+/UIbn+fl9BQrfQCsA2ZQw6joRKfzTQOfqYzDN+IW21tLjGW+MnIHZgBknhiZmnHCLB0MoF70F6kQyIO1eYA3rKqpwQE6QliSVzyL107yP+uC/kktQHtt9eg31AUSgaAJUBV2aR+h6FZRKtx07hcFytI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602226912; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0xuDhV6d86IPXH2GY4IaI9H9gj6ruJ1VR1dBduL9MKU=; b=eKMrTuCUA/43QdBGb52XBI8WARKnGAmm92TGx0PUU2m+FWyJ+JQfnVdI0VuRh3T5kDF70/peLu0rviQ/StmS0XhvvgvQP8CuOtdcLWrGnzbfPU5NN5LKXRTftLy/QocbBBBccmuBTH8zErcpU+Wj4/DNmNmN2147yq6WMSwClHM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160222691298472.62224409605187; Fri, 9 Oct 2020 00:01:52 -0700 (PDT) Received: from localhost ([::1]:60670 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmPX-00080x-Nc for importer@patchew.org; Fri, 09 Oct 2020 03:01:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAI-00062O-7U; Fri, 09 Oct 2020 02:46:07 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4775 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAF-0001JD-AD; Fri, 09 Oct 2020 02:46:05 -0400 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B0986A1A668D3492D030; Fri, 9 Oct 2020 14:45:59 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:49 +0800 From: zhaolichang To: Subject: [PATCH V2 02/14] ppc/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:37 +0800 Message-ID: <20201009064449.2336-3-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= ppc. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Acked-by: David Gibson Reviewed-by: Greg Kurz Reviewed-by: Thomas Huth --- target/ppc/cpu.h | 6 +++--- target/ppc/excp_helper.c | 6 +++--- target/ppc/fpu_helper.c | 2 +- target/ppc/internal.h | 2 +- target/ppc/kvm.c | 2 +- target/ppc/machine.c | 2 +- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu_helper.c | 4 ++-- target/ppc/translate_init.c.inc | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 766e9c5c26..ba5ebb13fc 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -615,7 +615,7 @@ enum { #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int= ) */ #define FPSCR_VE 7 /* Floating-point invalid operation exception enab= le */ #define FPSCR_OE 6 /* Floating-point overflow exception enable = */ -#define FPSCR_UE 5 /* Floating-point undeflow exception enable = */ +#define FPSCR_UE 5 /* Floating-point underflow exception enable = */ #define FPSCR_ZE 4 /* Floating-point zero divide exception enable = */ #define FPSCR_XE 3 /* Floating-point inexact exception enable = */ #define FPSCR_NI 2 /* Floating-point non-IEEE mode = */ @@ -2331,13 +2331,13 @@ enum { /* Internal hardware exception sources */ PPC_INTERRUPT_DECR, /* Decrementer exception = */ PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception = */ - PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt = */ + PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt= */ PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt = */ PPC_INTERRUPT_WDT, /* Watchdog timer interrupt = */ PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt = */ PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt = */ PPC_INTERRUPT_PERFM, /* Performance monitor interrupt = */ - PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt = */ + PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ }; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a988ba15f4..d7411bcc81 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -231,7 +231,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) } =20 /* - * Exception targetting modifiers + * Exception targeting modifiers * * LPES0 is supported on POWER7/8/9 * LPES1 is not supported (old iSeries mode) @@ -1015,7 +1015,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) * This means we will incorrectly execute past the power management * instruction instead of triggering a reset. * - * It generally means a discrepancy between the wakup conditions i= n the + * It generally means a discrepancy between the wakeup conditions = in the * processor has_work implementation and the logic in this functio= n. */ cpu_abort(env_cpu(env), @@ -1191,7 +1191,7 @@ void helper_rfi(CPUPPCState *env) void helper_rfid(CPUPPCState *env) { /* - * The architeture defines a number of rules for which bits can + * The architecture defines a number of rules for which bits can * change but in practice, we handle this in hreg_store_msr() * which will be called by do_rfi(), so there is no need to filter * here diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ae43b08eb5..9b8c8b70b6 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -1804,7 +1804,7 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t o= p1, uint64_t op2) =20 =20 /* - * VSX_ADD_SUB - VSX floating point add/subract + * VSX_ADD_SUB - VSX floating point add/subtract * name - instruction mnemonic * op - operation (add or sub) * nels - number of elements (1, 2 or 4) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 15d655b356..b4df127f4a 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -1,5 +1,5 @@ /* - * PowerPC interal definitions for qemu. + * PowerPC internal definitions for qemu. * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d85ba8ffe0..e85ef2ea9e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -487,7 +487,7 @@ int kvm_arch_init_vcpu(CPUState *cs) /* * KVM-HV has transactional memory on POWER8 also without * the KVM_CAP_PPC_HTM extension, so enable it here - * instead as long as it's availble to userspace on the + * instead as long as it's available to userspace on the * host. */ if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 109d071162..f6a24a9c9a 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -337,7 +337,7 @@ static int cpu_post_load(void *opaque, int version_id) =20 /* * If we're operating in compat mode, we should be ok as long as - * the destination supports the same compatiblity mode. + * the destination supports the same compatibility mode. * * Otherwise, however, we require that the destination has exactly * the same CPU model as the source. diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c31d21e6a9..977b2d1561 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -883,7 +883,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, /* * Note on LPCR usage: 970 uses HID4, but our special variant of * store_spr copies relevant fields into env->spr[SPR_LPCR]. - * Similarily we filter unimplemented bits when storing into LPCR + * Similarly we filter unimplemented bits when storing into LPCR * depending on the MMU version. This code can thus just use the * LPCR "as-is". */ diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 8972714775..50aa18a763 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -179,7 +179,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, = target_ulong pte0, } /* Compute access rights */ access =3D pp_check(ctx->key, pp, ctx->nx); - /* Keep the matching PTE informations */ + /* Keep the matching PTE information */ ctx->raddr =3D pte1; ctx->prot =3D access; ret =3D check_prot(ctx->prot, rw, type); @@ -2176,7 +2176,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong s= rnum, target_ulong value) env->sr[srnum] =3D value; /* * Invalidating 256MB of virtual memory in 4kB pages is way - * longer than flusing the whole TLB. + * longer than flushing the whole TLB. */ #if !defined(FLUSH_ALL_TLBS) && 0 { diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index bb66526280..3e0810fd6d 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -792,7 +792,7 @@ static void gen_spr_generic(CPUPPCState *env) &spr_read_xer, &spr_write_xer, &spr_read_xer, &spr_write_xer, 0x00000000); - /* Branch contol */ + /* Branch control */ spr_register(env, SPR_LR, "LR", &spr_read_lr, &spr_write_lr, &spr_read_lr, &spr_write_lr, --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602226644; cv=none; d=zohomail.com; s=zohoarc; b=Fo/JjWaiDQhy5Kv87wbWYkYpWfo2cS/cfqKcvoLJLM5MXQwrQ2IBIAHO2PYvOv2DbUXEZd1A0IrWz8HLiOoKpT6+zlAsizAz1zkokABBVhJPo6YF4eF68c8sWxqIP9Zk0ZV8cwI9Twu8kyID52wBDrmeWqLRZ649ecODVJN0KTg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602226644; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OqeawYdf0LYXfwoTmAD/ivQP9MxuRT6Z01WR33DXHMM=; b=Qrs0lHYUloeAyqZV6fEwUsyEXxC4cRuW/ReBNJR/V5xSCUNXD3Fe/ZS8tSl/liPY31PvAL6SWQFjgfQcPwNe4nMA1njbymHmFfKiqr8nLYsc7nPHOYB/Pqh08C3ev9dOk3r+QrIO+vkcawG/0G0Wk3BL8Er1dlJgm56IDhC8tXg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602226644498922.1869574173148; Thu, 8 Oct 2020 23:57:24 -0700 (PDT) Received: from localhost ([::1]:47022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmLD-000220-8e for importer@patchew.org; Fri, 09 Oct 2020 02:57:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAG-0005xw-9f; Fri, 09 Oct 2020 02:46:04 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55030 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAE-0001J8-5C; Fri, 09 Oct 2020 02:46:03 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 28578F2F243A03987B3E; Fri, 9 Oct 2020 14:45:58 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:51 +0800 From: zhaolichang To: Subject: [PATCH V2 03/14] riscv/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:38 +0800 Message-ID: <20201009064449.2336-4-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:58 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , Alistair Francis , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= riscv. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 2 +- target/riscv/cpu_bits.h | 2 +- target/riscv/csr.c | 6 +++--- target/riscv/vector_helper.c | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0bbfd7f457..f40a0b26a3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -472,7 +472,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) return; } } else { - qemu_log("vector verison is not specified, " + qemu_log("vector version is not specified, " "use the default value v0.7.1\n"); } set_vext_version(env, vext_version); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index bd36062877..6e1155560b 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -536,7 +536,7 @@ /* Leaf page shift amount */ #define PGSHIFT 12 =20 -/* Default Reset Vector adress */ +/* Default Reset Vector address */ #define DEFAULT_RSTVEC 0x1000 =20 /* Exception causes */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aaef6c6f20..93e117020d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -624,7 +624,7 @@ static int write_mcounteren(CPURISCVState *env, int csr= no, target_ulong val) return 0; } =20 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { @@ -634,7 +634,7 @@ static int read_mscounteren(CPURISCVState *env, int csr= no, target_ulong *val) return 0; } =20 -/* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ +/* This register is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */ static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong v= al) { if (env->priv_ver < PRIV_VERSION_1_11_0) { @@ -1278,7 +1278,7 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target= _ulong *ret_value, !riscv_cpu_virt_enabled(env)) { /* * We are in S mode without virtualisation, therefore we are in HS= Mode. - * Add 1 to the effective privledge level to allow us to access the + * Add 1 to the effective privilege level to allow us to access the * Hypervisor CSRs. */ effective_priv++; diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index a156573d28..fa89a6e6c1 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -709,7 +709,7 @@ typedef void vext_amo_noatomic_fn(void *vs3, target_ulo= ng addr, uint32_t wd, uint32_t idx, CPURISCVState= *env, uintptr_t retaddr); =20 -/* no atomic opreation for vector atomic insructions */ +/* no atomic operation for vector atomic insructions */ #define DO_SWAP(N, M) (M) #define DO_AND(N, M) (N & M) #define DO_XOR(N, M) (N ^ M) --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602227010; cv=none; d=zohomail.com; s=zohoarc; b=gtFkikvirDiXkRBZoIdkRDUlKV5DNyzPezrJWzTC/GNK21BqEi+OrbiTjydY5BpTFwSOFnSgSsoMnp5P8wGCRS/+V22pGap7jhvboCQ0o9v4FjMpPym9CXR2/odysUk6W0CmjLt5NK8ZLkb0+iqWg3MTgyF5wn50s4pPQkgoKfM= ARC-Message-Signature: i=1; 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Fri, 09 Oct 2020 03:03:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56246) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAK-00063I-FC; Fri, 09 Oct 2020 02:46:08 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5210 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAI-0001JS-CH; Fri, 09 Oct 2020 02:46:08 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 0CC368D2AD7916C895B5; Fri, 9 Oct 2020 14:46:03 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:53 +0800 From: zhaolichang To: Subject: [PATCH V2 04/14] rx/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:39 +0800 Message-ID: <20201009064449.2336-5-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= rx. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/rx/op_helper.c | 2 +- target/rx/translate.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index f89d294f2b..59389f4992 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -318,7 +318,7 @@ void helper_swhile(CPURXState *env, uint32_t sz) env->psw_c =3D (tmp <=3D env->regs[2]); } =20 -/* accumlator operations */ +/* accumulator operations */ void helper_rmpa(CPURXState *env, uint32_t sz) { uint64_t result_l, prev; diff --git a/target/rx/translate.c b/target/rx/translate.c index 482278edd2..9ea941c630 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -1089,7 +1089,7 @@ static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) tcg_gen_xor_i32(temp, arg1, arg2); tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); tcg_temp_free_i32(temp); - /* CMP not requred return */ + /* CMP not required return */ if (ret) { tcg_gen_mov_i32(ret, cpu_psw_s); } --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602226496; cv=none; d=zohomail.com; s=zohoarc; b=MQrIXPy/ezKtu4+ryeBeHFw67tUFI+mRzGqbSdxyaHUOjPxwElAck+vArbt6oFYz86RNEhSe1a/xDhfBXhm2Soul4eX/D3608EcMvhj0eLWLx8LQotVMGVLDo5jApBBBcdTiEv/AquwxTaPg9cctKDW9N8STHHU/oS5iieiajO4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602226496; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IgSP98NVcQ8pCWxYCIiRQcnt8lIPHewIsKn5lcGAdqE=; b=QwzZr4GO/sKE0bUhIPVaP77tUPEqEloldqAaTPH7YSof0IULjgp/cB2YJp02F2wob3A9/qmWxGyTpRNxhKZ/GuaUEDpn/ov+IZAdeRuKJz2ZZYjUW4J/A8VE3nTnYdWe+COsydjCLB7kwsXLJUUymoGqDGFkf7DYaf3jJ6DqskU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602226496298422.0744817783336; Thu, 8 Oct 2020 23:54:56 -0700 (PDT) Received: from localhost ([::1]:37746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmIo-0006Tl-Vo for importer@patchew.org; Fri, 09 Oct 2020 02:54:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-00064p-GN; Fri, 09 Oct 2020 02:46:17 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5211 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAK-0001Ja-GL; Fri, 09 Oct 2020 02:46:15 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id DE5DE287C44E90277BEA; Fri, 9 Oct 2020 14:46:03 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:54 +0800 From: zhaolichang To: Subject: [PATCH V2 05/14] tricore/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:40 +0800 Message-ID: <20201009064449.2336-6-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= tricore. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson --- target/s390x/ioinst.c | 2 +- target/tricore/csfr.def | 2 +- target/tricore/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/s390x/ioinst.c b/target/s390x/ioinst.c index a412926d27..c576d85e57 100644 --- a/target/s390x/ioinst.c +++ b/target/s390x/ioinst.c @@ -279,7 +279,7 @@ void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, u= int32_t ipb, /* * As operand exceptions have a lower priority than access excepti= ons, * we check whether the memory area is writeable (injecting the - * access execption if it is not) first. + * access exception if it is not) first. */ if (!s390_cpu_virt_mem_check_write(cpu, addr, ar, sizeof(schib))) { s390_program_interrupt(env, PGM_OPERAND, ra); diff --git a/target/tricore/csfr.def b/target/tricore/csfr.def index ff004cbddc..cdfaf1d662 100644 --- a/target/tricore/csfr.def +++ b/target/tricore/csfr.def @@ -1,4 +1,4 @@ -/* A(ll) access permited +/* A(ll) access permitted R(ead only) access E(nd init protected) access =20 diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 7752630ac1..c9c420d9d7 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -397,7 +397,7 @@ static inline void gen_mfcr(DisasContext *ctx, TCGv ret= , int32_t offset) #undef E =20 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg, - since no execption occurs */ + since no exception occurs */ #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \ case ADDRESS: \ if (has_feature(ctx, FEATURE)) { \ --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 8 Oct 2020 23:52:21 -0700 (PDT) Received: from localhost ([::1]:59230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmGJ-0003ZA-TP for importer@patchew.org; Fri, 09 Oct 2020 02:52:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-00064N-2I; Fri, 09 Oct 2020 02:46:16 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55124 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAJ-0001JX-Gd; Fri, 09 Oct 2020 02:46:10 -0400 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A13BBF941449DCC8CF80; Fri, 9 Oct 2020 14:46:03 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:56 +0800 From: zhaolichang To: Subject: [PATCH V2 06/14] mips/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:41 +0800 Message-ID: <20201009064449.2336-7-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:58 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= mips. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/mips/internal.h | 2 +- target/mips/translate.c | 10 +++++----- target/mips/translate_init.c.inc | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/mips/internal.h b/target/mips/internal.h index 7f159a9230..b811f547f3 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -188,7 +188,7 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMI= PSState *env) /* * A MIPS configured with a vectorizing external interrupt control= ler * will feed a vector into the Cause pending lines. The core treats - * the status lines as a vector level, not as indiviual masks. + * the status lines as a vector level, not as individual masks. */ r =3D pending > status; } else { diff --git a/target/mips/translate.c b/target/mips/translate.c index 398edf7289..b4d009078e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -3718,7 +3718,7 @@ static void gen_st_cond(DisasContext *ctx, int rt, in= t base, int offset, =20 t0 =3D tcg_temp_new(); addr =3D tcg_temp_new(); - /* compare the address against that of the preceeding LL */ + /* compare the address against that of the preceding LL */ gen_base_offset_addr(ctx, addr, base, offset); tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1); tcg_temp_free(addr); @@ -25597,7 +25597,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) } /* return resulting half-words to its original position */ tcg_gen_shri_i32(t0, t0, 16); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); =20 tcg_temp_free(t1); @@ -25633,7 +25633,7 @@ static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) } /* return resulting half-words to its original position */ tcg_gen_shri_i32(t0, t0, 16); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); =20 tcg_temp_free(t1); @@ -25702,7 +25702,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) } /* return resulting byte to its original position */ tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } =20 @@ -25742,7 +25742,7 @@ static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) } /* return resulting byte to its original position */ tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); - /* finaly update the destination */ + /* finally update the destination */ tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); } =20 diff --git a/target/mips/translate_init.c.inc b/target/mips/translate_init.= c.inc index 637caccd89..c735b2bf66 100644 --- a/target/mips/translate_init.c.inc +++ b/target/mips/translate_init.c.inc @@ -995,7 +995,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def= _t *def) =20 /* MVPConf1 implemented, TLB sharable, no gating storage support, programmable cache partitioning implemented, number of allocatable - and sharable TLB entries, MVP has allocatable TCs, 2 VPEs + and shareable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ env->mvp->CP0_MVPConf0 =3D (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 9 Oct 2020 00:00:04 -0700 (PDT) Received: from localhost ([::1]:56126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmNn-0005y4-5M for importer@patchew.org; Fri, 09 Oct 2020 03:00:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56302) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAU-00065K-Fk; Fri, 09 Oct 2020 02:46:20 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:5162 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAM-0001Jp-S5; Fri, 09 Oct 2020 02:46:18 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B65DFF7FCAA9C07AA396; Fri, 9 Oct 2020 14:46:06 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:57 +0800 From: zhaolichang To: Subject: [PATCH V2 07/14] s390x/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:42 +0800 Message-ID: <20201009064449.2336-8-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:16 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= s390x. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Thomas Huth --- target/s390x/cpu_models.h | 4 ++-- target/s390x/excp_helper.c | 2 +- target/s390x/fpu_helper.c | 2 +- target/s390x/insn-data.def | 2 +- target/s390x/misc_helper.c | 2 +- target/s390x/translate.c | 4 ++-- target/s390x/translate_vx.c.inc | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/target/s390x/cpu_models.h b/target/s390x/cpu_models.h index 74d1f87e4f..15c0f0dcfe 100644 --- a/target/s390x/cpu_models.h +++ b/target/s390x/cpu_models.h @@ -24,13 +24,13 @@ struct S390CPUDef { uint8_t gen; /* hw generation identification */ uint16_t type; /* cpu type identification */ uint8_t ec_ga; /* EC GA version (on which also the BC is base= d) */ - uint8_t mha_pow; /* Maximum Host Adress Power, mha =3D 2^pow-1 = */ + uint8_t mha_pow; /* Maximum Host Address Power, mha =3D 2^pow-1= */ uint32_t hmfai; /* hypervisor-managed facilities */ /* base/min features, must never be changed between QEMU versions */ S390FeatBitmap base_feat; /* used to init base_feat from generated data */ S390FeatInit base_init; - /* deafault features, QEMU version specific */ + /* default features, QEMU version specific */ S390FeatBitmap default_feat; /* used to init default_feat from generated data */ S390FeatInit default_init; diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index 0adfbbda27..36ab5c7c43 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -538,7 +538,7 @@ try_deliver: /* don't trigger a cpu_loop_exit(), use an interrupt instead */ cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HALT); } else if (cs->halted) { - /* unhalt if we had a WAIT PSW somehwere in our injection chain */ + /* unhalt if we had a WAIT PSW somewhere in our injection chain */ s390_cpu_unhalt(cpu); } } diff --git a/target/s390x/fpu_helper.c b/target/s390x/fpu_helper.c index f155bc048c..3e609b7fd0 100644 --- a/target/s390x/fpu_helper.c +++ b/target/s390x/fpu_helper.c @@ -89,7 +89,7 @@ static void handle_exceptions(CPUS390XState *env, bool Xx= C, uintptr_t retaddr) /* * invalid/divbyzero cannot coexist with other conditions. * overflow/underflow however can coexist with inexact, we have to - * handle it separatly. + * handle it separately. */ if (s390_exc & ~S390_IEEE_MASK_INEXACT) { if (s390_exc & ~S390_IEEE_MASK_INEXACT & env->fpc >> 24) { diff --git a/target/s390x/insn-data.def b/target/s390x/insn-data.def index d3bcdfd67b..2469415319 100644 --- a/target/s390x/insn-data.def +++ b/target/s390x/insn-data.def @@ -526,7 +526,7 @@ /* LOAD LOGICAL HALFWORD RELATIVE LONG */ C(0xc402, LLHRL, RIL_b, GIE, 0, ri2, new, r1_32, ld16u, 0) C(0xc406, LLGHRL, RIL_b, GIE, 0, ri2, r1, 0, ld16u, 0) -/* LOAD LOGICAL IMMEDATE */ +/* LOAD LOGICAL IMMEDIATE */ D(0xc00e, LLIHF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 32) D(0xc00f, LLILF, RIL_a, EI, 0, i2_32u_shl, 0, r1, mov2, 0, 0) D(0xa50c, LLIHH, RI_a, Z, 0, i2_16u_shl, 0, r1, mov2, 0, 48) diff --git a/target/s390x/misc_helper.c b/target/s390x/misc_helper.c index 58dbc023eb..929e509519 100644 --- a/target/s390x/misc_helper.c +++ b/target/s390x/misc_helper.c @@ -312,7 +312,7 @@ uint32_t HELPER(stsi)(CPUS390XState *env, uint64_t a0, = uint64_t r0, uint64_t r1) /* same as machine type number in STORE CPU ID, but in EBCDIC = */ snprintf(type, ARRAY_SIZE(type), "%X", cpu->model->def->type); ebcdic_put(sysib.sysib_111.type, type, 4); - /* model number (not stored in STORE CPU ID for z/Architecure)= */ + /* model number (not stored in STORE CPU ID for z/Architecture= ) */ ebcdic_put(sysib.sysib_111.model, "QEMU ", 16); ebcdic_put(sysib.sysib_111.sequence, "QEMU ", 16); ebcdic_put(sysib.sysib_111.plant, "QEMU", 4); diff --git a/target/s390x/translate.c b/target/s390x/translate.c index ac10f42f10..4395455e0a 100644 --- a/target/s390x/translate.c +++ b/target/s390x/translate.c @@ -433,7 +433,7 @@ static void gen_program_exception(DisasContext *s, int = code) { TCGv_i32 tmp; =20 - /* Remember what pgm exeption this was. */ + /* Remember what pgm exception this was. */ tmp =3D tcg_const_i32(code); tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUS390XState, int_pgm_code)); tcg_temp_free_i32(tmp); @@ -489,7 +489,7 @@ static TCGv_i64 get_address(DisasContext *s, int x2, in= t b2, int d2) =20 /* * Note that d2 is limited to 20 bits, signed. If we crop negative - * displacements early we create larger immedate addends. + * displacements early we create larger immediate addends. */ if (b2 && x2) { tcg_gen_add_i64(tmp, regs[b2], regs[x2]); diff --git a/target/s390x/translate_vx.c.inc b/target/s390x/translate_vx.c.= inc index eb767f5288..983da56b9d 100644 --- a/target/s390x/translate_vx.c.inc +++ b/target/s390x/translate_vx.c.inc @@ -789,7 +789,7 @@ static DisasJumpType op_vpk(DisasContext *s, DisasOps *= o) } break; case 0x94: - /* If sources and destination dont't overlap -> fast path */ + /* If sources and destination don't overlap -> fast path */ if (v1 !=3D v2 && v1 !=3D v3) { const uint8_t src_es =3D get_field(s, m4); const uint8_t dst_es =3D src_es - 1; --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602226988; cv=none; d=zohomail.com; s=zohoarc; b=BXRmshfbRGLnucY+tzKbwhAyCK0qCg21YeeqOojW28pkCtWTslcLXCEm+HxpD4RLGKXpBwbrYXdtMeSVUChtYslbLdgVRD4OxZG3j6PsA09yH5zIxlJYAqW/VQxt1t1PVGVQw1CnRyrpr4Fs8gVuJMavR5cTULj+QQ1nL1/9obE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602226988; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5KoCb65tq8btxEpCIBI2VSwjQ4abl59+V41riq2d4mA=; b=LRhmXbNG/rrESBMSQ6pvcOpaOYhNqGsOArVg0lViSdQW5fNyZhbhnNe2CWppz3l1Ubo0zjP+m/KTpt9UNPNbTNw8fs8PxKkAQfTsWEe/Br6PGv10TPKAPmyGBaiyfxl6+Xwp8IvXdMlwSBkQAoz+zC8wmqEH2BgSdJiN7gqnhGw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602226988751252.65737899805254; Fri, 9 Oct 2020 00:03:08 -0700 (PDT) Received: from localhost ([::1]:35956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmQl-0001EF-Eh for importer@patchew.org; Fri, 09 Oct 2020 03:03:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56370) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAe-00068o-39; Fri, 09 Oct 2020 02:46:28 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:55224 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001K2-IA; Fri, 09 Oct 2020 02:46:27 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id DB459A45892EB9F0360D; Fri, 9 Oct 2020 14:46:07 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:58 +0800 From: zhaolichang To: Subject: [PATCH V2 08/14] m68k/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:43 +0800 Message-ID: <20201009064449.2336-9-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:58 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , Laurent Vivier , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= m68k. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude Reviewed-by: Laurent Vivier Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/m68k/translate.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 3fc67aa452..133a404919 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -438,7 +438,7 @@ static TCGv gen_addr_index(DisasContext *s, uint16_t ex= t, TCGv tmp) } =20 /* - * Handle a base + index + displacement effective addresss. + * Handle a base + index + displacement effective address. * A NULL_QREG base means pc-relative. */ static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base) @@ -1696,7 +1696,7 @@ static void bcd_add(TCGv dest, TCGv src) =20 /* * t1 =3D (src + 0x066) + dest + X - * =3D result with some possible exceding 0x6 + * =3D result with some possible exceeding 0x6 */ =20 t0 =3D tcg_const_i32(0x066); @@ -1706,7 +1706,7 @@ static void bcd_add(TCGv dest, TCGv src) tcg_gen_add_i32(t1, t0, dest); tcg_gen_add_i32(t1, t1, QREG_CC_X); =20 - /* we will remove exceding 0x6 where there is no carry */ + /* we will remove exceeding 0x6 where there is no carry */ =20 /* * t0 =3D (src + 0x0066) ^ dest @@ -1736,7 +1736,7 @@ static void bcd_add(TCGv dest, TCGv src) tcg_temp_free(t0); =20 /* - * remove the exceding 0x6 + * remove the exceeding 0x6 * for digits that have not generated a carry */ =20 @@ -2638,7 +2638,7 @@ DISAS_INSN(negx) gen_flush_flags(s); /* compute old Z */ =20 /* - * Perform substract with borrow. + * Perform subtract with borrow. * (X, N) =3D -(src + X); */ =20 @@ -2653,7 +2653,7 @@ DISAS_INSN(negx) /* * Compute signed-overflow for negation. The normal formula for * subtraction is (res ^ src) & (src ^ dest), but with dest=3D=3D0 - * this simplies to res & src. + * this simplifies to res & src. */ =20 tcg_gen_and_i32(QREG_CC_V, QREG_CC_N, src); @@ -3159,7 +3159,7 @@ static inline void gen_subx(DisasContext *s, TCGv src= , TCGv dest, int opsize) gen_flush_flags(s); /* compute old Z */ =20 /* - * Perform substract with borrow. + * Perform subtract with borrow. * (X, N) =3D dest - (src + X); */ =20 @@ -3169,7 +3169,7 @@ static inline void gen_subx(DisasContext *s, TCGv src= , TCGv dest, int opsize) gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1); tcg_gen_andi_i32(QREG_CC_X, QREG_CC_X, 1); =20 - /* Compute signed-overflow for substract. */ + /* Compute signed-overflow for subtract. */ =20 tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, dest); tcg_gen_xor_i32(tmp, dest, src); --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602226638; cv=none; d=zohomail.com; s=zohoarc; b=Wg0TeawMVeVFZfL4O98eh3kpMNdi2+EGQvQB2IijEFcx0kx26XGCKTRrkrus4CvaHPEt+N/+hPh4RTKEnBXDAsfu7uZpky+CoLXJsG9fwwa9JmuzHe/twWCGEjpXTXODHkBOtd+dSwrWZOJ541jhzy/YVAgsYx6b03s7oDGDEX4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602226638; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EdEKptnbbcZl8dSqucVBFGuh09NbN0uEqwv+WM6GO7Y=; b=h4VJzLfalhzwCj287MmNOVlsV15cxOJ8nt4iw1tzROOWqu0OCE/mrC6/YS7yh+o6p7PZmBxXgoneFwrSC02O7SjYZcy9dYBzfQ2VMVOBXQhDCXvlcvLoD+NTa4bLINvGB+2cJk7aSbWK8LHFaSfcHBwYbEuju3dikCGxlPUEj6o= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602226638989240.92947582942645; Thu, 8 Oct 2020 23:57:18 -0700 (PDT) Received: from localhost ([::1]:46560 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmL7-0001qU-OG for importer@patchew.org; Fri, 09 Oct 2020 02:57:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56336) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAX-00066R-74; Fri, 09 Oct 2020 02:46:21 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:5163 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001K8-Gv; Fri, 09 Oct 2020 02:46:20 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 00A93FCF439F12BC3E80; Fri, 9 Oct 2020 14:46:09 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:45:58 +0800 From: zhaolichang To: Subject: [PATCH V2 09/14] sh4/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:44 +0800 Message-ID: <20201009064449.2336-10-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:16 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= sh4. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/sh4/cpu.h | 2 +- target/sh4/op_helper.c | 2 +- target/sh4/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dbe58c7888..91fa9498f0 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -160,7 +160,7 @@ typedef struct CPUSH4State { uint32_t pteh; /* page table entry high register */ uint32_t ptel; /* page table entry low register */ uint32_t ptea; /* page table entry assistance register */ - uint32_t ttb; /* tranlation table base register */ + uint32_t ttb; /* translation table base register */ uint32_t tea; /* TLB exception address register */ uint32_t tra; /* TRAPA exception register */ uint32_t expevt; /* exception event register */ diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c index 14c3db0f48..9de4152735 100644 --- a/target/sh4/op_helper.c +++ b/target/sh4/op_helper.c @@ -400,7 +400,7 @@ float32 helper_fsrra_FT(CPUSH4State *env, float32 t0) t0 =3D float32_div(float32_one, t0, &env->fp_status); /* Since this is supposed to be an approximation, an imprecision exception is required. One supposes this also follows the usual - IEEE rule that other exceptions take precidence. */ + IEEE rule that other exceptions take precedence. */ if (get_float_exception_flags(&env->fp_status) =3D=3D 0) { set_float_exception_flags(float_flag_inexact, &env->fp_status); } diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 60c863d9e1..c57218eb7d 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -1959,7 +1959,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4Stat= e *env) NEXT_INSN; switch (ctx->opcode & 0xf00f) { case 0x6003: /* mov Rm,Rn */ - /* Here we want to recognize ld_dst being saved for later consumti= on, + /* Here we want to recognize ld_dst being saved for later consumpt= ion, or for another input register being copied so that ld_dst need = not be clobbered during the operation. */ op_dst =3D B11_8; --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602227055; cv=none; d=zohomail.com; s=zohoarc; b=Og52DmhTxHw5B5wdkWL5stpHOoxvs1mstGqhQrycfV61znIwWZlFc1ca2XGr6TTFQTwEhwrpSAkP5ssHLXmpRo54uyqgMjayLRse8AnETv2vFyR4swQGC8oztirRQZoXB/WqntKeGy8SPx8B/FYG22KD0MNfrHOtlq+tO0MK0I4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602227055; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zlv4DM+bn26/m5co9bXfP0huYob8ywOeczeKlMn5MXY=; b=GS2wnoXfoNdXhgI+6rbgMsJRAKpDDY0o49s5SbpG2An9Y0tA+Z1vojhRl9tf+sX8R5x9dsHvdxtR0PzZ7spoiwawGAmR05rZhID0lNjLFZv1p9WBTOl/I6K5R6nJPh4DERDn0c8HP2Wv9LnhE4KiUusJbtditiH8SxCtZem+zq0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602227055034702.7332525113108; Fri, 9 Oct 2020 00:04:15 -0700 (PDT) Received: from localhost ([::1]:39758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmRp-0002oU-DG for importer@patchew.org; Fri, 09 Oct 2020 03:04:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56346) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAY-00066v-FU; Fri, 09 Oct 2020 02:46:26 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:38566 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001Jw-45; Fri, 09 Oct 2020 02:46:22 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 481517CB3C467CBC3AEB; Fri, 9 Oct 2020 14:46:07 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:46:00 +0800 From: zhaolichang To: Subject: [PATCH V2 10/14] i386/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:45 +0800 Message-ID: <20201009064449.2336-11-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:46:07 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= i386. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson --- target/i386/cpu.c | 4 ++-- target/i386/hax-interface.h | 4 ++-- target/i386/hax-windows.c | 2 +- target/i386/kvm.c | 2 +- target/i386/machine.c | 6 +++--- target/i386/translate.c | 8 ++++---- target/i386/whpx-all.c | 2 +- 7 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f37eb7b675..79ecb1c370 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -4677,7 +4677,7 @@ static const char *x86_cpu_feature_name(FeatureWord w= , int bitnr) return name; } =20 -/* Compatibily hack to maintain legacy +-feat semantic, +/* Compatibility hack to maintain legacy +-feat semantic, * where +-feat overwrites any feature set by * feat=3Don|feat even if the later is parsed after +-feat * (i.e. "-x2apic,x2apic=3Don" will result in x2apic disabled) @@ -6898,7 +6898,7 @@ static void x86_cpu_get_crash_info_qom(Object *obj, V= isitor *v, GuestPanicInformation *panic_info; =20 if (!cs->crash_occurred) { - error_setg(errp, "No crash occured"); + error_setg(errp, "No crash occurred"); return; } =20 diff --git a/target/i386/hax-interface.h b/target/i386/hax-interface.h index 537ae084e9..edef4fdf5d 100644 --- a/target/i386/hax-interface.h +++ b/target/i386/hax-interface.h @@ -238,7 +238,7 @@ enum exit_status { HAX_EXIT_UNKNOWN_VMEXIT, /* HALT from guest */ HAX_EXIT_HLT, - /* Reboot request, like because of tripple fault in guest */ + /* Reboot request, like because of triple fault in guest */ HAX_EXIT_STATECHANGE, /* the vcpu is now only paused when destroy, so simply return to hax */ HAX_EXIT_PAUSED, @@ -295,7 +295,7 @@ struct hax_qemu_version { uint32_t min_version; } __attribute__ ((__packed__)); =20 -/* The mac specfic interface to qemu, mostly is ioctl related */ +/* The mac specific interface to qemu, mostly is ioctl related */ struct hax_tunnel_info { uint64_t va; uint64_t io_va; diff --git a/target/i386/hax-windows.c b/target/i386/hax-windows.c index 6c82dfb54f..4297c457a2 100644 --- a/target/i386/hax-windows.c +++ b/target/i386/hax-windows.c @@ -174,7 +174,7 @@ int hax_mod_version(struct hax_state *hax, struct hax_m= odule_version *version) if (!ret) { err =3D GetLastError(); if (err =3D=3D ERROR_INSUFFICIENT_BUFFER || err =3D=3D ERROR_MORE_= DATA) { - fprintf(stderr, "hax module verion is too long to hold.\n"); + fprintf(stderr, "hax module version is too long to hold.\n"); } fprintf(stderr, "Failed to get Hax module version:%lu\n", err); return -EFAULT; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 8b12387d30..e97315f394 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -1164,7 +1164,7 @@ static int hv_cpuid_check_and_set(CPUState *cs, struc= t kvm_cpuid2 *cpuid, /* * Fill in Hyper-V CPUIDs. Returns the number of entries filled in cpuid_e= nt in * case of success, errno < 0 in case of failure and 0 when no Hyper-V - * extentions are enabled. + * extensions are enabled. */ static int hyperv_handle_properties(CPUState *cs, struct kvm_cpuid_entry2 *cpuid_ent) diff --git a/target/i386/machine.c b/target/i386/machine.c index 233e46bb70..03af4a1e5f 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -264,12 +264,12 @@ static int cpu_pre_save(void *opaque) * hypervisor, its exception payload (CR2/DR6 on #PF/#DB) * should not be set yet in the respective vCPU register. * Thus, in case an exception is pending, it is - * important to save the exception payload seperately. + * important to save the exception payload separately. * * Therefore, if an exception is not in a pending state * or vCPU is not in guest-mode, it is not important to * distinguish between a pending and injected exception - * and we don't need to store seperately the exception payload. + * and we don't need to store separately the exception payload. * * In order to preserve better backwards-compatible migration, * convert a pending exception to an injected exception in @@ -1156,7 +1156,7 @@ static int nested_state_post_load(void *opaque, int v= ersion_id) return -EINVAL; } if (nested_state->size > max_nested_state_len) { - error_report("Recieved unsupported nested state size: " + error_report("Received unsupported nested state size: " "nested_state->size=3D%d, max=3D%d", nested_state->size, max_nested_state_len); return -EINVAL; diff --git a/target/i386/translate.c b/target/i386/translate.c index caea6f5fb1..5cdfe0ebc4 100644 --- a/target/i386/translate.c +++ b/target/i386/translate.c @@ -893,7 +893,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, = TCGv reg) } =20 /* perform a conditional store into register 'reg' according to jump opcode - value 'b'. In the fast case, T0 is guaranted not to be used. */ + value 'b'. In the fast case, T0 is guaranteed not to be used. */ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) { int inv, jcc_op, cond; @@ -1026,7 +1026,7 @@ static inline void gen_compute_eflags_c(DisasContext = *s, TCGv reg) } =20 /* generate a conditional jump to label 'l1' according to jump opcode - value 'b'. In the fast case, T0 is guaranted not to be used. */ + value 'b'. In the fast case, T0 is guaranteed not to be used. */ static inline void gen_jcc1_noeob(DisasContext *s, int b, TCGLabel *l1) { CCPrepare cc =3D gen_prepare_cc(s, b, s->T0); @@ -1043,7 +1043,7 @@ static inline void gen_jcc1_noeob(DisasContext *s, in= t b, TCGLabel *l1) } =20 /* Generate a conditional jump to label 'l1' according to jump opcode - value 'b'. In the fast case, T0 is guaranted not to be used. + value 'b'. In the fast case, T0 is guaranteed not to be used. A translation block must end soon. */ static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1) { @@ -6841,7 +6841,7 @@ static target_ulong disas_insn(DisasContext *s, CPUSt= ate *cpu) if (s->prefix & PREFIX_LOCK) { switch (op) { case 0: /* bt */ - /* Needs no atomic ops; we surpressed the normal + /* Needs no atomic ops; we suppressed the normal memory load for LOCK above so do it now. */ gen_op_ld_v(s, ot, s->T0, s->A0); break; diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c index f4f3e33eac..9127c2749d 100644 --- a/target/i386/whpx-all.c +++ b/target/i386/whpx-all.c @@ -1235,7 +1235,7 @@ int whpx_init_vcpu(CPUState *cpu) vcpu =3D g_malloc0(sizeof(struct whpx_vcpu)); =20 if (!vcpu) { - error_report("WHPX: Failed to allocte VCPU context."); + error_report("WHPX: Failed to allocate VCPU context."); ret =3D -ENOMEM; goto error; } --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602227184; cv=none; d=zohomail.com; s=zohoarc; b=PMwPbN0qfvmX3mbRgq6bNo86sDEi+mH2aDSJQlkR91PlXEyRRXntTbDVhdx5y3kbCU5MOOxFWKcVrThuy/bZimad3albz0K3e/Q/FhGK26queuFMAYxe2aw8Q4a1UqwpDXxKngb6slV/FLTK8XBz2M3YpICZf2Vh3GtlzyglRGk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602227184; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CcopPxB0+M79Fw6oMVKcUpiSw3EDRwThoulipkd95Ug=; b=nXRs9NYtojnvbwKWRIAGRQqlU4MngSuYq2fuMEjyuVvL5rtVZQAo5v1farp74BFHJFL5PGFjhLHQtH/42Xeo31nAJ462yx/7BgPCSqCtWnaLigRKqTAS4GwpGcRvHne0u2Hh4YtvS5q+Hg1HMtRxK6fkVntqh/A3Tlyn2lgVRLo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602227184860356.2439442723271; Fri, 9 Oct 2020 00:06:24 -0700 (PDT) Received: from localhost ([::1]:46222 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmTv-0005aE-Iz for importer@patchew.org; Fri, 09 Oct 2020 03:06:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56358) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAc-00067B-Ko; Fri, 09 Oct 2020 02:46:27 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:38664 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001KJ-IJ; Fri, 09 Oct 2020 02:46:26 -0400 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 75E7FDC111935BA085E0; Fri, 9 Oct 2020 14:46:11 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:46:01 +0800 From: zhaolichang To: Subject: [PATCH V2 11/14] avr/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:46 +0800 Message-ID: <20201009064449.2336-12-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:46:07 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= avr. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/avr/helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c index d96d14372b..9f325bc1d8 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -97,7 +97,7 @@ int avr_cpu_memory_rw_debug(CPUState *cs, vaddr addr, uin= t8_t *buf, =20 hwaddr avr_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) { - return addr; /* I assume 1:1 address correspondance */ + return addr; /* I assume 1:1 address correspondence */ } =20 bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -298,7 +298,7 @@ void helper_outb(CPUAVRState *env, uint32_t port, uint3= 2_t data) } =20 /* - * this function implements LD instruction when there is a posibility to = read + * this function implements LD instruction when there is a possibility to= read * from a CPU register */ target_ulong helper_fullrd(CPUAVRState *env, uint32_t addr) @@ -322,7 +322,7 @@ target_ulong helper_fullrd(CPUAVRState *env, uint32_t a= ddr) } =20 /* - * this function implements ST instruction when there is a posibility to = write + * this function implements ST instruction when there is a possibility to= write * into a CPU register */ void helper_fullwr(CPUAVRState *env, uint32_t data, uint32_t addr) --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602227314; cv=none; d=zohomail.com; s=zohoarc; b=MwlJy1vAlZLo7aHto2wyS3F6dXd9II84WAeo7SwELeO8dUaidkyhWQHxANJXBKNTAPKe0RKo7If5UEPsyTKkVuQtbPySA2+4hXF62W+kQvdJu+qq64ZGJOkGwuo7O2AEV9XyhKryIcMLWeVvPvOaAL5L4OUN+fx5Knz2ilnT9mg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602227314; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=IcRlcaqQNO1czgvJliIEsRtdROFIpHJyTmzcHD886w4=; b=A/r3cU7m198uxt1Vwpznyc355s4ykABaY+APXaBjAHywo4eB5JnwXSfukHvqDIlSQLnzbMMysyEoPSp2LlVT4KrquTQqqaCdGXRdxqpA4WAk+vZ1IsPh5lHFbkxitPUBRfNIadXPAxmGfMMLFOzWlYC1/a+k1dc83QJrFQxszdI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602227314246940.0267497625829; Fri, 9 Oct 2020 00:08:34 -0700 (PDT) Received: from localhost ([::1]:52400 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmW0-00088B-VE for importer@patchew.org; Fri, 09 Oct 2020 03:08:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56386) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAe-0006A9-LT; Fri, 09 Oct 2020 02:46:28 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:5164 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001K7-I9; Fri, 09 Oct 2020 02:46:28 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id EFAC5E88C67239AC7086; Fri, 9 Oct 2020 14:46:08 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:46:02 +0800 From: zhaolichang To: Subject: [PATCH V2 12/14] arm/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:47 +0800 Message-ID: <20201009064449.2336-13-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:16 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= arm. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/arm/cpu.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 2 +- target/arm/translate-a64.c | 4 ++-- target/arm/translate-sve.c | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfff1b5c8f..985f6834a4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2090,7 +2090,7 @@ static inline bool arm_el_is_aa64(CPUARMState *env, i= nt el) return aa64; } =20 -/* Function for determing whether guest cp register reads and writes should +/* Function for determining whether guest cp register reads and writes sho= uld * access the secure or non-secure bank of a cp register. When EL3 is * operating in AArch32 state, the NS-bit determines whether the secure * instance of a cp register should be used. When EL3 is AArch64 (or if diff --git a/target/arm/helper.c b/target/arm/helper.c index cd0779ff5f..a23dfdec07 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1868,7 +1868,7 @@ static void pmevtyper_rawwrite(CPUARMState *env, cons= t ARMCPRegInfo *ri, * pmevtyper_rawwrite is called between a pair of pmu_op_start and * pmu_op_finish calls when loading saved state for a migration. Becau= se * we're potentially updating the type of event here, the value writte= n to - * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a + * c14_pmevcntr_delta by the preceding pmu_op_start call may be for a * different counter type. Therefore, we need to set this value to the * current count for the counter type we're writing so that pmu_op_fin= ish * has the correct count for its calculation. @@ -12216,7 +12216,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, } else { memattr =3D 0x44; /* Normal, NC, No */ } - cacheattrs->shareability =3D 2; /* outer sharable */ + cacheattrs->shareability =3D 2; /* outer shareable */ } else { memattr =3D 0x00; /* Device, nGnRnE */ } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 036454234c..1e8080dc92 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -158,7 +158,7 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr= , uint32_t op) * R: 0 because unpriv and A flag not set * SRVALID: 0 because NS * MRVALID: 0 because unpriv and A flag not set - * SREGION: 0 becaus SRVALID is 0 + * SREGION: 0 because SRVALID is 0 * MREGION: 0 because MRVALID is 0 */ return 0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7188808341..5451f02995 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -160,7 +160,7 @@ void gen_a64_set_pc_im(uint64_t val) * + for EL2 and EL3 there is only one TBI bit, and if it is set * then the address is zero-extended, clearing bits [63:56] * + for EL0 and EL1, TBI0 controls addresses with bit 55 =3D=3D 0 - * and TBI1 controls addressses with bit 55 =3D=3D 1. + * and TBI1 controls addresses with bit 55 =3D=3D 1. * If the appropriate TBI bit is set for the address then * the address is sign-extended from bit 55 into bits [63:56] * @@ -1964,7 +1964,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* - * A write to any coprocessor regiser that ends a TB + * A write to any coprocessor register that ends a TB * must rebuild the hflags for the next TB. */ TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 9095586fc9..73b0686213 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1528,7 +1528,7 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *= a) =20 /* Perform an inline saturating addition of a 32-bit value within * a 64-bit register. The second operand is known to be positive, - * which halves the comparisions we must perform to bound the result. + * which halves the comparisons we must perform to bound the result. */ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) { --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602227119; cv=none; d=zohomail.com; s=zohoarc; b=hFkhBGHdrsoUi8uKe3Wcg43DXEXcBiSoo7JGBm64iu0EOXLefsjDYiXsGmAfskefqwfblxU7Xq+UnarZzePUDtNoBCb2/6RnK6SMCu1vXwx6Bma4M4YFE+oJMGYB6CtxcGM1Grzo5S6niPT49TV+bCv66nX2qyOtoTVoCwl6XhU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602227119; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jI8eIQT/F2hjByWCaFfY2e9yg/WYh39fId7bbw072QE=; b=QE3q5KDuXjwa1SYNfXwcQFnKGeQMFORtQe0gQ4XSWgg/nG99iCXXO+3mJuPRU7wfrQiO0y9a7AX13/LA7bcObd6StjrOPrH7osLbesfxwFPK0ENUrJOdquQWJvJh3LWwPnGAmnvxAw3OdF6MM/pYii0I12jWPqReRa9LogZDBYY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1602227119218217.44577084006403; Fri, 9 Oct 2020 00:05:19 -0700 (PDT) Received: from localhost ([::1]:42268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmSr-0003qT-Q7 for importer@patchew.org; Fri, 09 Oct 2020 03:05:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAe-0006AO-P0; Fri, 09 Oct 2020 02:46:28 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5212 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001KP-IQ; Fri, 09 Oct 2020 02:46:28 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 36D08C9986D155A49FE2; Fri, 9 Oct 2020 14:46:13 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:46:03 +0800 From: zhaolichang To: Subject: [PATCH V2 13/14] alpha/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:48 +0800 Message-ID: <20201009064449.2336-14-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= alpha. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/alpha/cpu.h | 4 ++-- target/alpha/translate.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index be29bdd530..8a6d47783a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -190,7 +190,7 @@ enum { =20 That said, we're only emulating Unix PALcode, and not attempting VMS, so we don't need to implement Executive and Supervisor. QEMU's own - PALcode cheats and usees the KSEG mapping for its code+data rather than + PALcode cheats and uses the KSEG mapping for its code+data rather than physical addresses. */ =20 #define MMU_KERNEL_IDX 0 @@ -370,7 +370,7 @@ enum { The Unix PALcode only uses bit 4. */ #define PS_USER_MODE 8u =20 -/* CPUAlphaState->flags constants. These are layed out so that we +/* CPUAlphaState->flags constants. These are laid out so that we can set or reset the pieces individually by assigning to the byte, or manipulated as a whole. */ =20 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 36be602179..c88ba38bc0 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -2940,7 +2940,7 @@ static void alpha_tr_init_disas_context(DisasContextB= ase *dcbase, CPUState *cpu) the first fp insn of the TB. Alternately we could define a proper default for every TB (e.g. QUAL_RM_N or QUAL_RM_D) and make sure to reset the FP_STATUS to that default at the end of any TB that - changes the default. We could even (gasp) dynamiclly figure out + changes the default. We could even (gasp) dynamically figure out what default would be most efficient given the running program. */ ctx->tb_rm =3D -1; /* Similarly for flush-to-zero. */ --=20 2.26.2.windows.1 From nobody Fri May 17 07:55:51 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1602227250; cv=none; d=zohomail.com; s=zohoarc; b=IMCyd9ptpCOPNRnsuz6YvDWWucjyNmXD0wr6WXNf6D3UHzTU+EIoIAzFQ4LqMnendxWlfIJROeYcKtR+exnb9ups49RZf3qriWy2/u+JQuFwdERj9ij+cwIk+vFiWIhEeK5pjyIrUVpctdGtAZp943yqb/XhN2W/x0om3pTJ0Co= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1602227250; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Pb+na/2bW7yQCXSK1kOqJrnLoY1a9QcbgTVBYQT66Wc=; b=jBSW797p5qf4MvtJEDgvj58h0a2YDaL7cc+DoIG/OQ5vG8rWcpHm46FiAvKZb00Wz1qS0N4+Z9CRHQRyu2sn2mViEprXqM+Xo0xOq0dgvDywZe8OwdNPLcUwM+BfZaljJkdPq5RLZlkyAqDaKrBPo4n1FRFalkDCHD/jWq4eDFM= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16022272504684.091132993200176; Fri, 9 Oct 2020 00:07:30 -0700 (PDT) Received: from localhost ([::1]:48590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kQmUz-0006Xn-44 for importer@patchew.org; Fri, 09 Oct 2020 03:07:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56398) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAf-0006B6-05; Fri, 09 Oct 2020 02:46:29 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5213 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kQmAS-0001KR-Jy; Fri, 09 Oct 2020 02:46:28 -0400 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 3BAF7A5FC36138034763; Fri, 9 Oct 2020 14:46:13 +0800 (CST) Received: from localhost (10.174.186.238) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.487.0; Fri, 9 Oct 2020 14:46:04 +0800 From: zhaolichang To: Subject: [PATCH V2 14/14] target/: fix some comment spelling errors Date: Fri, 9 Oct 2020 14:44:49 +0800 Message-ID: <20201009064449.2336-15-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20201009064449.2336-1-zhaolichang@huawei.com> References: <20201009064449.2336-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.186.238] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/09 02:45:42 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Edmondson , zhaolichang , qemu-devel@nongnu.org, Philippe Mathieu-Daude Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson Reviewed-by: Philippe Mathieu-Daude --- target/openrisc/cpu.h | 2 +- target/sparc/asi.h | 2 +- target/unicore32/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bd42faf144..8ca8605301 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -291,7 +291,7 @@ typedef struct CPUOpenRISCState { int is_counting; =20 uint32_t picmr; /* Interrupt mask register */ - uint32_t picsr; /* Interrupt contrl register*/ + uint32_t picsr; /* Interrupt control register*/ #endif void *irq[32]; /* Interrupt irq input */ } CPUOpenRISCState; diff --git a/target/sparc/asi.h b/target/sparc/asi.h index bb58735ddb..4e9f1d59ed 100644 --- a/target/sparc/asi.h +++ b/target/sparc/asi.h @@ -231,7 +231,7 @@ #define ASI_INTR_ID 0x63 /* (CMT) Interrupt ID register */ #define ASI_CORE_ID 0x63 /* (CMT) LP ID register */ #define ASI_CESR_ID 0x63 /* (CMT) CESR ID register */ -#define ASI_IC_INSTR 0x66 /* Insn cache instrucion ram diag */ +#define ASI_IC_INSTR 0x66 /* Insn cache instruction ram diag */ #define ASI_IC_TAG 0x67 /* Insn cache tag/valid ram diag */ #define ASI_IC_STAG 0x68 /* (III) Insn cache snoop tag ram */ #define ASI_IC_PRE_DECODE 0x6e /* Insn cache pre-decode ram diag */ diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index d4b06df672..2e91b05c15 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -119,7 +119,7 @@ static void load_reg_var(DisasContext *s, TCGv var, int= reg) { if (reg =3D=3D 31) { uint32_t addr; - /* normaly, since we updated PC */ + /* normally, since we updated PC */ addr =3D (long)s->pc; tcg_gen_movi_i32(var, addr); } else { --=20 2.26.2.windows.1