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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/11] tcg: Remove TCG_CT_REG
Date: Thu, 8 Oct 2020 07:56:52 -0500
Message-Id: <20201008125659.49857-5-richard.henderson@linaro.org>
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This wasn't actually used for anything, really. All variable
operands must accept registers, and which are indicated by the
set in TCGArgConstraint.regs.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 1 -
tcg/tcg.c | 15 ++++-----------
tcg/aarch64/tcg-target.c.inc | 3 ---
tcg/arm/tcg-target.c.inc | 3 ---
tcg/i386/tcg-target.c.inc | 11 -----------
tcg/mips/tcg-target.c.inc | 3 ---
tcg/ppc/tcg-target.c.inc | 5 -----
tcg/riscv/tcg-target.c.inc | 2 --
tcg/s390/tcg-target.c.inc | 4 ----
tcg/sparc/tcg-target.c.inc | 5 -----
tcg/tci/tcg-target.c.inc | 1 -
11 files changed, 4 insertions(+), 49 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 63955ac85b..3168315bb8 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -979,7 +979,6 @@ void tcg_dump_op_count(void);
#define TCG_CT_ALIAS 0x80
#define TCG_CT_IALIAS 0x40
#define TCG_CT_NEWREG 0x20 /* output requires a new register */
-#define TCG_CT_REG 0x01
#define TCG_CT_CONST 0x02 /* any constant of register size */
=20
typedef struct TCGArgConstraint {
diff --git a/tcg/tcg.c b/tcg/tcg.c
index da01e39fe4..55b2fc3ae3 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -2194,21 +2194,14 @@ static void tcg_dump_ops(TCGContext *s, bool have_p=
refs)
/* we give more priority to constraints with less registers */
static int get_constraint_priority(const TCGOpDef *def, int k)
{
- const TCGArgConstraint *arg_ct;
+ const TCGArgConstraint *arg_ct =3D &def->args_ct[k];
+ int n;
=20
- int i, n;
- arg_ct =3D &def->args_ct[k];
if (arg_ct->ct & TCG_CT_ALIAS) {
/* an alias is equivalent to a single register */
n =3D 1;
} else {
- if (!(arg_ct->ct & TCG_CT_REG))
- return 0;
- n =3D 0;
- for(i =3D 0; i < TCG_TARGET_NB_REGS; i++) {
- if (tcg_regset_test_reg(arg_ct->regs, i))
- n++;
- }
+ n =3D ctpop64(arg_ct->regs);
}
return TCG_TARGET_NB_REGS - n + 1;
}
@@ -2276,7 +2269,7 @@ static void process_op_defs(TCGContext *s)
int oarg =3D *ct_str - '0';
tcg_debug_assert(ct_str =3D=3D tdefs->args_ct_str[=
i]);
tcg_debug_assert(oarg < def->nb_oargs);
- tcg_debug_assert(def->args_ct[oarg].ct & TCG_CT_RE=
G);
+ tcg_debug_assert(def->args_ct[oarg].regs !=3D 0);
/* TCG_CT_ALIAS is for the output arguments.
The input is tagged with TCG_CT_IALIAS. */
def->args_ct[i] =3D def->args_ct[oarg];
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index dbe5c6a14c..26f71cb599 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -128,15 +128,12 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
{
switch (*ct_str++) {
case 'r': /* general registers */
- ct->ct |=3D TCG_CT_REG;
ct->regs |=3D 0xffffffffu;
break;
case 'w': /* advsimd registers */
- ct->ct |=3D TCG_CT_REG;
ct->regs |=3D 0xffffffff00000000ull;
break;
case 'l': /* qemu_ld / qemu_st address, data_reg */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffffu;
#ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry,
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 978eb1dd70..62c37a954b 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -253,13 +253,11 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
break;
=20
case 'r':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffff;
break;
=20
/* qemu_ld address */
case 'l':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffff;
#ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry,
@@ -274,7 +272,6 @@ static const char *target_parse_constraint(TCGArgConstr=
aint *ct,
=20
/* qemu_st address & data */
case 's':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu o=
nly)
and r0-r1 doing the byte swapping, so don't use these. */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 8661ec3393..2f696074ab 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -208,42 +208,33 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
{
switch(*ct_str++) {
case 'a':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
break;
case 'b':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
break;
case 'c':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
break;
case 'd':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
break;
case 'S':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
break;
case 'D':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
break;
case 'q':
/* A register that can be used as a byte operand. */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xf;
break;
case 'Q':
/* A register with an addressable second byte (e.g. %ah). */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xf;
break;
case 'r':
/* A general register. */
- ct->ct |=3D TCG_CT_REG;
ct->regs |=3D ALL_GENERAL_REGS;
break;
case 'W':
@@ -252,13 +243,11 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
break;
case 'x':
/* A vector register. */
- ct->ct |=3D TCG_CT_REG;
ct->regs |=3D ALL_VECTOR_REGS;
break;
=20
/* qemu_ld/st address constraint */
case 'L':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D TCG_TARGET_REG_BITS =3D=3D 64 ? 0xffff : 0xff;
tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index aae4fd187b..41be574e89 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -195,11 +195,9 @@ static const char *target_parse_constraint(TCGArgConst=
raint *ct,
{
switch(*ct_str++) {
case 'r':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
break;
case 'L': /* qemu_ld input arg constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
@@ -209,7 +207,6 @@ static const char *target_parse_constraint(TCGArgConstr=
aint *ct,
#endif
break;
case 'S': /* qemu_st constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU)
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 0bd947b788..18ee989f95 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -224,19 +224,15 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
{
switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D':
- ct->ct |=3D TCG_CT_REG;
tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break;
case 'r':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
break;
case 'v':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff00000000ull;
break;
case 'L': /* qemu_ld constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
@@ -245,7 +241,6 @@ static const char *target_parse_constraint(TCGArgConstr=
aint *ct,
#endif
break;
case 'S': /* qemu_st constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 0a69839adb..d536f3ccc1 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -137,12 +137,10 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
{
switch (*ct_str++) {
case 'r':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
break;
case 'L':
/* qemu_ld/qemu_st constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
/* qemu_ld/qemu_st uses TCG_REG_TMP0 */
#if defined(CONFIG_SOFTMMU)
diff --git a/tcg/s390/tcg-target.c.inc b/tcg/s390/tcg-target.c.inc
index 9cd266a2d0..c5e096449b 100644
--- a/tcg/s390/tcg-target.c.inc
+++ b/tcg/s390/tcg-target.c.inc
@@ -408,23 +408,19 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
{
switch (*ct_str++) {
case 'r': /* all registers */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffff;
break;
case 'L': /* qemu_ld/st constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffff;
tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break;
case 'a': /* force R2 for division */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break;
case 'b': /* force R3 for division */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0;
tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break;
diff --git a/tcg/sparc/tcg-target.c.inc b/tcg/sparc/tcg-target.c.inc
index e2de749af7..6775bd30fc 100644
--- a/tcg/sparc/tcg-target.c.inc
+++ b/tcg/sparc/tcg-target.c.inc
@@ -325,15 +325,12 @@ static const char *target_parse_constraint(TCGArgCons=
traint *ct,
{
switch (*ct_str++) {
case 'r':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
break;
case 'R':
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D ALL_64;
break;
case 'A': /* qemu_ld/st address constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D TARGET_LONG_BITS =3D=3D 64 ? ALL_64 : 0xffffffff;
reserve_helpers:
tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
@@ -341,11 +338,9 @@ static const char *target_parse_constraint(TCGArgConst=
raint *ct,
tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
break;
case 's': /* qemu_st data 32-bit constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D 0xffffffff;
goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D ALL_64;
goto reserve_helpers;
case 'I':
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index a7215f346f..231b9b1775 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -392,7 +392,6 @@ static const char *target_parse_constraint(TCGArgConstr=
aint *ct,
case 'r':
case 'L': /* qemu_ld constraint */
case 'S': /* qemu_st constraint */
- ct->ct |=3D TCG_CT_REG;
ct->regs =3D BIT(TCG_TARGET_NB_REGS) - 1;
break;
default:
--=20
2.25.1