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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/11] accel/tcg: Fix computing of is_write for MIPS
Date: Thu, 8 Oct 2020 07:56:59 -0500
Message-Id: <20201008125659.49857-12-richard.henderson@linaro.org>
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From: Kele Huang <kele.hwang@gmail.com>
Detect all MIPS store instructions in cpu_signal_handler for all available
MIPS versions, and set is_write if encountering such store instructions.
This fixed the error while dealing with self-modified code for MIPS.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Kele Huang <kele.hwang@gmail.com>
Signed-off-by: Xu Zou <iwatchnima@gmail.com>
Message-Id: <20201002081420.10814-1-kele.hwang@gmail.com>
[rth: Use uintptr_t for pc to fix n32 build error.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/user-exec.c | 43 +++++++++++++++++++++++++++++++++++++++----
1 file changed, 39 insertions(+), 4 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 5c96819ded..4ebe25461a 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -702,16 +702,51 @@ int cpu_signal_handler(int host_signum, void *pinfo,
=20
#elif defined(__mips__)
=20
+#if defined(__misp16) || defined(__mips_micromips)
+#error "Unsupported encoding"
+#endif
+
int cpu_signal_handler(int host_signum, void *pinfo,
void *puc)
{
siginfo_t *info =3D pinfo;
ucontext_t *uc =3D puc;
- greg_t pc =3D uc->uc_mcontext.pc;
- int is_write;
+ uintptr_t pc =3D uc->uc_mcontext.pc;
+ uint32_t insn =3D *(uint32_t *)pc;
+ int is_write =3D 0;
+
+ /* Detect all store instructions at program counter. */
+ switch((insn >> 26) & 077) {
+ case 050: /* SB */
+ case 051: /* SH */
+ case 052: /* SWL */
+ case 053: /* SW */
+ case 054: /* SDL */
+ case 055: /* SDR */
+ case 056: /* SWR */
+ case 070: /* SC */
+ case 071: /* SWC1 */
+ case 074: /* SCD */
+ case 075: /* SDC1 */
+ case 077: /* SD */
+#if !defined(__mips_isa_rev) || __mips_isa_rev < 6
+ case 072: /* SWC2 */
+ case 076: /* SDC2 */
+#endif
+ is_write =3D 1;
+ break;
+ case 023: /* COP1X */
+ /* Required in all versions of MIPS64 since
+ MIPS64r1 and subsequent versions of MIPS32r2. */
+ switch (insn & 077) {
+ case 010: /* SWXC1 */
+ case 011: /* SDXC1 */
+ case 015: /* SUXC1 */
+ is_write =3D 1;
+ }
+ break;
+ }
=20
- /* XXX: compute is_write */
- is_write =3D 0;
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
=20
--=20
2.25.1