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bh=hFnF9scAiMQ534Ar+rYpee7FQAMrzoQLMyIExVO/PwY=; b=dfAZnUABKqRJubwaQi/IcriwgQIr4BxTQEAzeEvSll8oRg/3JuCkhRYZ6dhfnQz6EtypGE jWb7IeXp4kPc0AGRvGOXNk7WvxpKp3tyi29tu2bK61m3iZFGWJAgruZxYIsELBtc9musIE dyRxVEYl2cHUNTPk5hQhtVvAHjQJAlQ= X-MC-Unique: EPdD8JVTNeGz7IL5Z_jIKw-1 From: John Snow To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 3/9] ide: rename cmd_write to ctrl_write Date: Thu, 1 Oct 2020 13:46:43 -0400 Message-Id: <20201001174649.1911016-4-jsnow@redhat.com> In-Reply-To: <20201001174649.1911016-1-jsnow@redhat.com> References: <20201001174649.1911016-1-jsnow@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.16 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jsnow@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=jsnow@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/01 04:25:37 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , John Snow , qemu-block@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) It's the Control register, part of the Control block -- Command is misleading here. Rename all related functions and constants. Signed-off-by: John Snow Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/ide/internal.h | 9 +++++---- hw/ide/core.c | 12 ++++++------ hw/ide/ioport.c | 2 +- hw/ide/macio.c | 2 +- hw/ide/mmio.c | 8 ++++---- hw/ide/pci.c | 12 ++++++------ hw/ide/trace-events | 2 +- 7 files changed, 24 insertions(+), 23 deletions(-) diff --git a/include/hw/ide/internal.h b/include/hw/ide/internal.h index 8a95ad8c4d3..a23bb2f3481 100644 --- a/include/hw/ide/internal.h +++ b/include/hw/ide/internal.h @@ -57,8 +57,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(IDEBus, IDE_BUS) #define REL 0x04 #define TAG_MASK 0xf8 =20 -#define IDE_CMD_RESET 0x04 -#define IDE_CMD_DISABLE_IRQ 0x02 +/* Bits of Device Control register */ +#define IDE_CTRL_RESET 0x04 +#define IDE_CTRL_DISABLE_IRQ 0x02 =20 /* ACS-2 T13/2015-D Table B.2 Command codes */ #define WIN_NOP 0x00 @@ -559,7 +560,7 @@ static inline IDEState *idebus_active_if(IDEBus *bus) =20 static inline void ide_set_irq(IDEBus *bus) { - if (!(bus->cmd & IDE_CMD_DISABLE_IRQ)) { + if (!(bus->cmd & IDE_CTRL_DISABLE_IRQ)) { qemu_irq_raise(bus->irq); } } @@ -598,7 +599,7 @@ void ide_atapi_io_error(IDEState *s, int ret); void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val); uint32_t ide_ioport_read(void *opaque, uint32_t addr1); uint32_t ide_status_read(void *opaque, uint32_t addr); -void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val); +void ide_ctrl_write(void *opaque, uint32_t addr, uint32_t val); void ide_data_writew(void *opaque, uint32_t addr, uint32_t val); uint32_t ide_data_readw(void *opaque, uint32_t addr); void ide_data_writel(void *opaque, uint32_t addr, uint32_t val); diff --git a/hw/ide/core.c b/hw/ide/core.c index f76f7e5234b..84499e2241c 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -2235,25 +2235,25 @@ uint32_t ide_status_read(void *opaque, uint32_t add= r) return ret; } =20 -void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val) +void ide_ctrl_write(void *opaque, uint32_t addr, uint32_t val) { IDEBus *bus =3D opaque; IDEState *s; int i; =20 - trace_ide_cmd_write(addr, val, bus); + trace_ide_ctrl_write(addr, val, bus); =20 /* common for both drives */ - if (!(bus->cmd & IDE_CMD_RESET) && - (val & IDE_CMD_RESET)) { + if (!(bus->cmd & IDE_CTRL_RESET) && + (val & IDE_CTRL_RESET)) { /* reset low to high */ for(i =3D 0;i < 2; i++) { s =3D &bus->ifs[i]; s->status =3D BUSY_STAT | SEEK_STAT; s->error =3D 0x01; } - } else if ((bus->cmd & IDE_CMD_RESET) && - !(val & IDE_CMD_RESET)) { + } else if ((bus->cmd & IDE_CTRL_RESET) && + !(val & IDE_CTRL_RESET)) { /* high to low */ for(i =3D 0;i < 2; i++) { s =3D &bus->ifs[i]; diff --git a/hw/ide/ioport.c b/hw/ide/ioport.c index ab1f4e5d9c0..b613ff3bbaf 100644 --- a/hw/ide/ioport.c +++ b/hw/ide/ioport.c @@ -46,7 +46,7 @@ static const MemoryRegionPortio ide_portio_list[] =3D { }; =20 static const MemoryRegionPortio ide_portio2_list[] =3D { - { 0, 1, 1, .read =3D ide_status_read, .write =3D ide_cmd_write }, + { 0, 1, 1, .read =3D ide_status_read, .write =3D ide_ctrl_write }, PORTIO_END_OF_LIST(), }; =20 diff --git a/hw/ide/macio.c b/hw/ide/macio.c index 62a599a0751..b270a101632 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -329,7 +329,7 @@ static void pmac_ide_write(void *opaque, hwaddr addr, u= int64_t val, case 0x8: case 0x16: if (size =3D=3D 1) { - ide_cmd_write(&d->bus, 0, val); + ide_ctrl_write(&d->bus, 0, val); } break; case 0x20: diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index 4bf6e3a8b76..36e2f4790ab 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -98,16 +98,16 @@ static uint64_t mmio_ide_status_read(void *opaque, hwad= dr addr, return ide_status_read(&s->bus, 0); } =20 -static void mmio_ide_cmd_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void mmio_ide_ctrl_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { MMIOState *s =3D opaque; - ide_cmd_write(&s->bus, 0, val); + ide_ctrl_write(&s->bus, 0, val); } =20 static const MemoryRegionOps mmio_ide_cs_ops =3D { .read =3D mmio_ide_status_read, - .write =3D mmio_ide_cmd_write, + .write =3D mmio_ide_ctrl_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 diff --git a/hw/ide/pci.c b/hw/ide/pci.c index b50091b615c..84ba733548e 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -38,7 +38,7 @@ (IDE_RETRY_DMA | IDE_RETRY_PIO | \ IDE_RETRY_READ | IDE_RETRY_FLUSH) =20 -static uint64_t pci_ide_cmd_read(void *opaque, hwaddr addr, unsigned size) +static uint64_t pci_ide_status_read(void *opaque, hwaddr addr, unsigned si= ze) { IDEBus *bus =3D opaque; =20 @@ -48,20 +48,20 @@ static uint64_t pci_ide_cmd_read(void *opaque, hwaddr a= ddr, unsigned size) return ide_status_read(bus, addr + 2); } =20 -static void pci_ide_cmd_write(void *opaque, hwaddr addr, - uint64_t data, unsigned size) +static void pci_ide_ctrl_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) { IDEBus *bus =3D opaque; =20 if (addr !=3D 2 || size !=3D 1) { return; } - ide_cmd_write(bus, addr + 2, data); + ide_ctrl_write(bus, addr + 2, data); } =20 const MemoryRegionOps pci_ide_cmd_le_ops =3D { - .read =3D pci_ide_cmd_read, - .write =3D pci_ide_cmd_write, + .read =3D pci_ide_status_read, + .write =3D pci_ide_ctrl_write, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 2e4162629f4..6e357685f9b 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -5,7 +5,7 @@ ide_ioport_read(uint32_t addr, const char *reg, uint32_t val, void *bus, v= oid *s) "IDE PIO rd @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState= %p" ide_ioport_write(uint32_t addr, const char *reg, uint32_t val, void *bus, = void *s) "IDE PIO wr @ 0x%"PRIx32" (%s); val 0x%02"PRIx32"; bus %p IDEState= %p" ide_status_read(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Alt Status); val 0x%02"PRIx32"; bus %p;= IDEState %p" -ide_cmd_write(uint32_t addr, uint32_t val, void *bus) = "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus= %p" +ide_ctrl_write(uint32_t addr, uint32_t val, void *bus) = "IDE PIO wr @ 0x%"PRIx32" (Device Control); val 0x%02"PRIx32"; bus= %p" # Warning: verbose ide_data_readw(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO rd @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p;= IDEState %p" ide_data_writew(uint32_t addr, uint32_t val, void *bus, void *s) = "IDE PIO wr @ 0x%"PRIx32" (Data: Word); val 0x%04"PRIx32"; bus %p;= IDEState %p" --=20 2.26.2