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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id 70sm342052wme.15.2020.10.01.07.48.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2020 07:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7IRmJR4QLq1yyKkeN0MLbFHRplQff2bZm6Ce52F5OFc=; b=K0wFdEMAOc+stAy/xWe+yZhe/qeJrWcAI6FXxTve7h6UUNibEs0StQhdGiheTC6xLt qSW9VrMhNbanDtzH1hbrKnA7a+GUSoPLbppFphN/2GcME/OlXO7PJwa0y8X2/6gSup6b nM/3Kv4jofGf/boWd5IKEfNANHuWlwE7PhFL57F/wzC1QJJVAfJMIxj3FYuGmXu63tBo 5efwdfvpqD/N4+fli7evo0loUFgW6aRg2+JBuO7kgnWFNdtjwWC1QRqgvBTnI4iLnHgt GRilFtx1vPk5IX66tkQ0Jd8+XnylOzPcHXGsP/Rf2CkrB+lv86ptiHAQQlGlnl0tZcKm 8kKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7IRmJR4QLq1yyKkeN0MLbFHRplQff2bZm6Ce52F5OFc=; b=dcpFULG6TGtsl5TQKC/JNZQ7BOpEJ7HGnYZL+cwJX1LyXDPztLhVt5tK4ct00V9N6S Rx31g2QMpugqEO8FelPpadfyvGNT7bnzYHAiW4ZnecwVkzGhCHJQmA1E7x9KYBXz+uxu VjrbulnrkFkpMYhjjeRzSbH1mUT4IDzCoZjyZCaqx8ZLb+gm9h/MmzMw8HO2fMqBuFLN usoY3VrTzprNA/XvaU3LDqrE8Fn0RXA7G+QfYz5J0kmeUFVxPpmEOwGSyKH6T4vz7S2W 70af1bBdOwB1sY3rF6ExFkJHo+WhFvrp3ECFR9rOn1K9AbwxBWoEfO7+UBBFzZ/X2SfO OCeg== X-Gm-Message-State: AOAM531ozUqWacADIv2/+UlpocXfriiPRGJyweRNrXPdav/hUQLjD+69 QUysO3CE+RDwUUAPKdXTvuaIqsizXcYEeue/ X-Google-Smtp-Source: ABdhPJy2D0tCtalSgxU8XAvJeJP54toi44akejCLNrejYTQqd+G/yPOOEpoJ4QYu2PoVx5OLqIMIeg== X-Received: by 2002:a5d:6551:: with SMTP id z17mr9450772wrv.200.1601563689663; Thu, 01 Oct 2020 07:48:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs Date: Thu, 1 Oct 2020 15:47:44 +0100 Message-Id: <20201001144759.5964-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20201001144759.5964-1-peter.maydell@linaro.org> References: <20201001144759.5964-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" M-profile CPUs only implement the ID registers as guest-visible if the CPU implements the Main Extension (all our current CPUs except the Cortex-M0 do). Currently we handle this by having the Cortex-M0 leave the ID register values in the ARMCPU struct as zero, but this conflicts with our design decision to make QEMU behaviour be keyed off ID register fields wherever possible. Explicitly code the ID registers in the NVIC to return 0 if the Main Extension is not implemented, so we can make the M0 model set the ARMCPU struct fields to obtain the correct behaviour without those values becoming guest-visible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200910173855.4068-4-peter.maydell@linaro.org --- hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a28be49c1e9..42b1ad59e65 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1238,32 +1238,74 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) "Aux Fault status registers unimplemented\n"); return 0; case 0xd40: /* PFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_pfr0; case 0xd44: /* PFR1. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_pfr1; case 0xd48: /* DFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->id_afr0; case 0xd50: /* MMFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr0; case 0xd54: /* MMFR1. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr1; case 0xd58: /* MMFR2. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr2; case 0xd5c: /* MMFR3. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr3; case 0xd60: /* ISAR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar0; case 0xd64: /* ISAR1. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar1; case 0xd68: /* ISAR2. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar2; case 0xd6c: /* ISAR3. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar3; case 0xd70: /* ISAR4. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar4; case 0xd74: /* ISAR5. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar5; case 0xd78: /* CLIDR */ return cpu->clidr; --=20 2.20.1