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bh=Dy0DQR+vsfbFZ1MRj051Z8ZJyIxAhZwRFkrx6m0gxQY=; b=a4GTc/K8ATY09akkp71z3Ci8WXVsUf2F/W+h4VytKvg6U3fF9D6hyNgFU3LKdFJUpZ5oom ebgOmaE5rJsjo7bddXsp2oLvMkAwQD0RnafOLugNjBTLyr+FrE9yXSYgDw5kQsY3zfWu/o /LYIchqcMK57+KvQ6pdjZb6lHacuyl8= X-MC-Unique: dtKyCU0BNiGUE1mGzKoLFg-1 From: Stefan Hajnoczi To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 04/17] block/nvme: Drop NVMeRegs structure, directly use NvmeBar Date: Wed, 30 Sep 2020 11:12:52 +0100 Message-Id: <20200930101305.305302-5-stefanha@redhat.com> In-Reply-To: <20200930101305.305302-1-stefanha@redhat.com> References: <20200930101305.305302-1-stefanha@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=stefanha@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Philippe Mathieu-Daud=C3=A9 NVMeRegs only contains NvmeBar. Simplify the code by using NvmeBar directly. This triggers a checkpatch.pl error: ERROR: Use of volatile is usually wrong, please add a comment #30: FILE: block/nvme.c:691: + volatile NvmeBar *regs; This is a false positive as in our case we are using I/O registers, so the 'volatile' use is justified. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Stefan Hajnoczi Message-Id: <20200922083821.578519-5-philmd@redhat.com> --- block/nvme.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index e517c7539f..bd82990b66 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -81,11 +81,6 @@ typedef struct { QEMUBH *completion_bh; } NVMeQueuePair; =20 -/* Memory mapped registers */ -typedef volatile struct { - NvmeBar ctrl; -} NVMeRegs; - #define INDEX_ADMIN 0 #define INDEX_IO(n) (1 + n) =20 @@ -694,7 +689,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, uint64_t timeout_ms; uint64_t deadline, now; Error *local_err =3D NULL; - NVMeRegs *regs; + volatile NvmeBar *regs =3D NULL; =20 qemu_co_mutex_init(&s->dma_map_lock); qemu_co_queue_init(&s->dma_flush_queue); @@ -722,7 +717,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, /* Perform initialize sequence as described in NVMe spec "7.6.1 * Initialization". */ =20 - cap =3D le64_to_cpu(regs->ctrl.cap); + cap =3D le64_to_cpu(regs->cap); if (!(cap & (1ULL << 37))) { error_setg(errp, "Device doesn't support NVMe command set"); ret =3D -EINVAL; @@ -735,10 +730,10 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, timeout_ms =3D MIN(500 * ((cap >> 24) & 0xFF), 30000); =20 /* Reset device to get a clean state. */ - regs->ctrl.cc =3D cpu_to_le32(le32_to_cpu(regs->ctrl.cc) & 0xFE); + regs->cc =3D cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE); /* Wait for CSTS.RDY =3D 0. */ deadline =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCA= LE_MS; - while (le32_to_cpu(regs->ctrl.csts) & 0x1) { + while (le32_to_cpu(regs->csts) & 0x1) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to reset (%" PRId64 " ms)", @@ -766,18 +761,18 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); - regs->ctrl.aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SI= ZE); - regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); - regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); + regs->aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE); + regs->asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); + regs->acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); =20 /* After setting up all control registers we can enable device now. */ - regs->ctrl.cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | + regs->cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 0x1); /* Wait for CSTS.RDY =3D 1. */ now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); deadline =3D now + timeout_ms * 1000000; - while (!(le32_to_cpu(regs->ctrl.csts) & 0x1)) { + while (!(le32_to_cpu(regs->csts) & 0x1)) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to start (%" PRId64 " ms)", --=20 2.26.2