From nobody Mon Feb 9 17:36:31 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1601459770; cv=none; d=zohomail.com; s=zohoarc; b=CAnh5jCHeZTrSxCB0yDPqydTHjiBWMkl3PQnwiug9TAqpO1YRs3VUCWTj3lzpXGUX5ygoBrfEWTVaj3PZuIDgowCgsIoQqF4wrKycVmliyurB0+7Ysc3K7wn1xi79SHxv6t2MQIQE+0XiKX5zgeVa9PSehJwik+kr/aoQYW/fN8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1601459770; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rVlj4N5enCTWSNc8QXifAtUVdKfgfC3t7RrBoynKSRE=; b=VPZrJLEQiPfYZjtJnfJHnkDqTU/+3mUSgAokuArUnsXig5JxcG/7yTXw01x042rDGGIcBo6s51OeKbEEptqYymIbdsrClCjjw1oL6NwQ6RWMC4mFr1HnPyuN+R02U9FMFP5BubvueD377vcu4dxSswaT5OCGWafMsI+945ZM4Yw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1601459770538875.6748798931469; Wed, 30 Sep 2020 02:56:10 -0700 (PDT) Received: from localhost ([::1]:43370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kNYqH-0000XF-6z for importer@patchew.org; Wed, 30 Sep 2020 05:56:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39284) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kNYoR-0007ET-Bj; Wed, 30 Sep 2020 05:54:15 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:49406 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kNYoO-0004Nb-Q9; Wed, 30 Sep 2020 05:54:15 -0400 Received: from DGGEMS412-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 40F958F80463C510D7AF; Wed, 30 Sep 2020 17:54:09 +0800 (CST) Received: from localhost (10.174.185.186) by DGGEMS412-HUB.china.huawei.com (10.3.19.212) with Microsoft SMTP Server id 14.3.487.0; Wed, 30 Sep 2020 17:54:01 +0800 From: zhaolichang To: Subject: [PATCH RFC 02/14] ppc/: fix some comment spelling errors Date: Wed, 30 Sep 2020 17:53:09 +0800 Message-ID: <20200930095321.2006-3-zhaolichang@huawei.com> X-Mailer: git-send-email 2.26.2.windows.1 In-Reply-To: <20200930095321.2006-1-zhaolichang@huawei.com> References: <20200930095321.2006-1-zhaolichang@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.186] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.35; envelope-from=zhaolichang@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/30 05:46:53 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhaolichang , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" I found that there are many spelling errors in the comments of qemu/target/= ppc. I used spellcheck to check the spelling errors and found some errors in the= folder. Signed-off-by: zhaolichang Reviewed-by: David Edmondson --- target/ppc/cpu.h | 6 +++--- target/ppc/excp_helper.c | 6 +++--- target/ppc/fpu_helper.c | 2 +- target/ppc/internal.h | 2 +- target/ppc/kvm.c | 2 +- target/ppc/machine.c | 2 +- target/ppc/mmu-hash64.c | 2 +- target/ppc/mmu_helper.c | 4 ++-- target/ppc/translate_init.c.inc | 2 +- 9 files changed, 14 insertions(+), 14 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 766e9c5..ba5ebb1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -615,7 +615,7 @@ enum { #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int= ) */ #define FPSCR_VE 7 /* Floating-point invalid operation exception enab= le */ #define FPSCR_OE 6 /* Floating-point overflow exception enable = */ -#define FPSCR_UE 5 /* Floating-point undeflow exception enable = */ +#define FPSCR_UE 5 /* Floating-point underflow exception enable = */ #define FPSCR_ZE 4 /* Floating-point zero divide exception enable = */ #define FPSCR_XE 3 /* Floating-point inexact exception enable = */ #define FPSCR_NI 2 /* Floating-point non-IEEE mode = */ @@ -2331,13 +2331,13 @@ enum { /* Internal hardware exception sources */ PPC_INTERRUPT_DECR, /* Decrementer exception = */ PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception = */ - PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt = */ + PPC_INTERRUPT_PIT, /* Programmable interval timer interrupt= */ PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt = */ PPC_INTERRUPT_WDT, /* Watchdog timer interrupt = */ PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt = */ PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt = */ PPC_INTERRUPT_PERFM, /* Performance monitor interrupt = */ - PPC_INTERRUPT_HMI, /* Hypervisor Maintainance interrupt = */ + PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ }; diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index a988ba1..d7411bc 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -231,7 +231,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) } =20 /* - * Exception targetting modifiers + * Exception targeting modifiers * * LPES0 is supported on POWER7/8/9 * LPES1 is not supported (old iSeries mode) @@ -1015,7 +1015,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) * This means we will incorrectly execute past the power management * instruction instead of triggering a reset. * - * It generally means a discrepancy between the wakup conditions i= n the + * It generally means a discrepancy between the wakeup conditions = in the * processor has_work implementation and the logic in this functio= n. */ cpu_abort(env_cpu(env), @@ -1191,7 +1191,7 @@ void helper_rfi(CPUPPCState *env) void helper_rfid(CPUPPCState *env) { /* - * The architeture defines a number of rules for which bits can + * The architecture defines a number of rules for which bits can * change but in practice, we handle this in hreg_store_msr() * which will be called by do_rfi(), so there is no need to filter * here diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index ae43b08..9b8c8b7 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -1804,7 +1804,7 @@ uint32_t helper_efdcmpeq(CPUPPCState *env, uint64_t o= p1, uint64_t op2) =20 =20 /* - * VSX_ADD_SUB - VSX floating point add/subract + * VSX_ADD_SUB - VSX floating point add/subtract * name - instruction mnemonic * op - operation (add or sub) * nels - number of elements (1, 2 or 4) diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 15d655b..b4df127 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -1,5 +1,5 @@ /* - * PowerPC interal definitions for qemu. + * PowerPC internal definitions for qemu. * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index d85ba8f..e85ef2e 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -487,7 +487,7 @@ int kvm_arch_init_vcpu(CPUState *cs) /* * KVM-HV has transactional memory on POWER8 also without * the KVM_CAP_PPC_HTM extension, so enable it here - * instead as long as it's availble to userspace on the + * instead as long as it's available to userspace on the * host. */ if (qemu_getauxval(AT_HWCAP2) & PPC_FEATURE2_HAS_HTM) { diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 109d071..f6a24a9 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -337,7 +337,7 @@ static int cpu_post_load(void *opaque, int version_id) =20 /* * If we're operating in compat mode, we should be ok as long as - * the destination supports the same compatiblity mode. + * the destination supports the same compatibility mode. * * Otherwise, however, we require that the destination has exactly * the same CPU model as the source. diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index c31d21e..977b2d1 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -883,7 +883,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr = eaddr, /* * Note on LPCR usage: 970 uses HID4, but our special variant of * store_spr copies relevant fields into env->spr[SPR_LPCR]. - * Similarily we filter unimplemented bits when storing into LPCR + * Similarly we filter unimplemented bits when storing into LPCR * depending on the MMU version. This code can thus just use the * LPCR "as-is". */ diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 8972714..50aa18a 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -179,7 +179,7 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, = target_ulong pte0, } /* Compute access rights */ access =3D pp_check(ctx->key, pp, ctx->nx); - /* Keep the matching PTE informations */ + /* Keep the matching PTE information */ ctx->raddr =3D pte1; ctx->prot =3D access; ret =3D check_prot(ctx->prot, rw, type); @@ -2176,7 +2176,7 @@ void helper_store_sr(CPUPPCState *env, target_ulong s= rnum, target_ulong value) env->sr[srnum] =3D value; /* * Invalidating 256MB of virtual memory in 4kB pages is way - * longer than flusing the whole TLB. + * longer than flushing the whole TLB. */ #if !defined(FLUSH_ALL_TLBS) && 0 { diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.= inc index bb66526..3e0810f 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -792,7 +792,7 @@ static void gen_spr_generic(CPUPPCState *env) &spr_read_xer, &spr_write_xer, &spr_read_xer, &spr_write_xer, 0x00000000); - /* Branch contol */ + /* Branch control */ spr_register(env, SPR_LR, "LR", &spr_read_lr, &spr_write_lr, &spr_read_lr, &spr_write_lr, --=20 2.26.2.windows.1