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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , Alistair Francis , Palmer Dabbelt , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Frank Chang helper_set_rounding_mode() is responsible for SIGILL, and "round to odd" should be an interface private to translation, so add a new independent helper_set_rod_rounding_mode(). Signed-off-by: Frank Chang --- target/riscv/fpu_helper.c | 5 +++++ target/riscv/helper.h | 1 + target/riscv/internals.h | 1 + target/riscv/translate.c | 5 +++++ 4 files changed, 12 insertions(+) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 3850146fec..b37e1d08a2 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,11 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32= _t rm) set_float_rounding_mode(softrm, &env->fp_status); } =20 +void helper_set_rod_rounding_mode(CPURISCVState *env) +{ + set_float_rounding_mode(float_round_to_odd, &env->fp_status); +} + static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 2a31c7bba1..32edc77858 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) =20 /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) =20 /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 55bcd84e39..f0705a796b 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -39,6 +39,7 @@ enum { RISCV_FRM_RUP =3D 3, /* Round Up */ RISCV_FRM_RMM =3D 4, /* Round to Nearest, ties to Max Magnitude */ RISCV_FRM_DYN =3D 7, /* Dynamic rounding mode */ + RISCV_FRM_ROD =3D 8, /* Round to Odd */ }; =20 static inline uint64_t nanbox_s(float32 f) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2d12b8adc4..e6f4a662f5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -30,6 +30,7 @@ #include "exec/log.h" =20 #include "instmap.h" +#include "internals.h" =20 /* global register indices */ static TCGv cpu_gpr[32], cpu_pc, cpu_vl; @@ -583,6 +584,10 @@ static void gen_set_rm(DisasContext *ctx, int rm) return; } ctx->frm =3D rm; + if (rm =3D=3D RISCV_FRM_ROD) { + gen_helper_set_rod_rounding_mode(cpu_env); + return; + } t0 =3D tcg_const_i32(rm); gen_helper_set_rounding_mode(cpu_env, t0); tcg_temp_free_i32(t0); --=20 2.17.1