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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=5334b480d=dmitry.fomichev@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/27 22:35:35 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Niklas Cassel , Damien Le Moal , qemu-block@nongnu.org, Dmitry Fomichev , qemu-devel@nongnu.org, Alistair Francis , Matias Bjorling Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Niklas Cassel Namespace Types introduce a new command set, "I/O Command Sets", that allows the host to retrieve the command sets associated with a namespace. Introduce support for the command set and enable detection for the NVM Command Set. The new workflows for identify commands rely heavily on zero-filled identify structs. E.g., certain CNS commands are defined to return a zero-filled identify struct when an inactive namespace NSID is supplied. Add a helper function in order to avoid code duplication when reporting zero-filled identify structures. Signed-off-by: Niklas Cassel Signed-off-by: Dmitry Fomichev --- hw/block/nvme-ns.c | 3 + hw/block/nvme.c | 210 +++++++++++++++++++++++++++++++++++++-------- 2 files changed, 175 insertions(+), 38 deletions(-) diff --git a/hw/block/nvme-ns.c b/hw/block/nvme-ns.c index bbd7879492..31b7f986c3 100644 --- a/hw/block/nvme-ns.c +++ b/hw/block/nvme-ns.c @@ -40,6 +40,9 @@ static void nvme_ns_init(NvmeNamespace *ns) =20 id_ns->nsze =3D cpu_to_le64(nvme_ns_nlbas(ns)); =20 + ns->params.csi =3D NVME_CSI_NVM; + qemu_uuid_generate(&ns->params.uuid); /* TODO make UUIDs persistent */ + /* no thin provisioning */ id_ns->ncap =3D id_ns->nsze; id_ns->nuse =3D id_ns->ncap; diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 29fa005fa2..4ec1ddc90a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1495,6 +1495,13 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeRequ= est *req) return NVME_SUCCESS; } =20 +static uint16_t nvme_rpt_empty_id_struct(NvmeCtrl *n, NvmeRequest *req) +{ + uint8_t id[NVME_IDENTIFY_DATA_SIZE] =3D {}; + + return nvme_dma(n, id, sizeof(id), DMA_DIRECTION_FROM_DEVICE, req); +} + static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeRequest *req) { trace_pci_nvme_identify_ctrl(); @@ -1503,11 +1510,23 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, Nvm= eRequest *req) DMA_DIRECTION_FROM_DEVICE, req); } =20 +static uint16_t nvme_identify_ctrl_csi(NvmeCtrl *n, NvmeRequest *req) +{ + NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; + + trace_pci_nvme_identify_ctrl_csi(c->csi); + + if (c->csi =3D=3D NVME_CSI_NVM) { + return nvme_rpt_empty_id_struct(n, req); + } + + return NVME_INVALID_FIELD | NVME_DNR; +} + static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeRequest *req) { NvmeNamespace *ns; NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; - NvmeIdNs *id_ns, inactive =3D { 0 }; uint32_t nsid =3D le32_to_cpu(c->nsid); =20 trace_pci_nvme_identify_ns(nsid); @@ -1518,23 +1537,46 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeR= equest *req) =20 ns =3D nvme_ns(n, nsid); if (unlikely(!ns)) { - id_ns =3D &inactive; - } else { - id_ns =3D &ns->id_ns; + return nvme_rpt_empty_id_struct(n, req); } =20 - return nvme_dma(n, (uint8_t *)id_ns, sizeof(NvmeIdNs), + return nvme_dma(n, (uint8_t *)&ns->id_ns, sizeof(NvmeIdNs), DMA_DIRECTION_FROM_DEVICE, req); } =20 +static uint16_t nvme_identify_ns_csi(NvmeCtrl *n, NvmeRequest *req) +{ + NvmeNamespace *ns; + NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; + uint32_t nsid =3D le32_to_cpu(c->nsid); + + trace_pci_nvme_identify_ns_csi(nsid, c->csi); + + if (!nvme_nsid_valid(n, nsid) || nsid =3D=3D NVME_NSID_BROADCAST) { + return NVME_INVALID_NSID | NVME_DNR; + } + + ns =3D nvme_ns(n, nsid); + if (unlikely(!ns)) { + return nvme_rpt_empty_id_struct(n, req); + } + + if (c->csi =3D=3D NVME_CSI_NVM) { + return nvme_rpt_empty_id_struct(n, req); + } + + return NVME_INVALID_FIELD | NVME_DNR; +} + static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeRequest *req) { + NvmeNamespace *ns; NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; - static const int data_len =3D NVME_IDENTIFY_DATA_SIZE; uint32_t min_nsid =3D le32_to_cpu(c->nsid); - uint32_t *list; - uint16_t ret; - int j =3D 0; + uint8_t list[NVME_IDENTIFY_DATA_SIZE] =3D {}; + static const int data_len =3D sizeof(list); + uint32_t *list_ptr =3D (uint32_t *)list; + int i, j =3D 0; =20 trace_pci_nvme_identify_nslist(min_nsid); =20 @@ -1548,48 +1590,76 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, N= vmeRequest *req) return NVME_INVALID_NSID | NVME_DNR; } =20 - list =3D g_malloc0(data_len); - for (int i =3D 1; i <=3D n->num_namespaces; i++) { - if (i <=3D min_nsid || !nvme_ns(n, i)) { + for (i =3D 1; i <=3D n->num_namespaces; i++) { + ns =3D nvme_ns(n, i); + if (!ns) { continue; } - list[j++] =3D cpu_to_le32(i); + if (ns->params.nsid < min_nsid) { + continue; + } + list_ptr[j++] =3D cpu_to_le32(ns->params.nsid); if (j =3D=3D data_len / sizeof(uint32_t)) { break; } } - ret =3D nvme_dma(n, (uint8_t *)list, data_len, DMA_DIRECTION_FROM_DEVI= CE, - req); - g_free(list); - return ret; + + return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req); +} + +static uint16_t nvme_identify_nslist_csi(NvmeCtrl *n, NvmeRequest *req) +{ + NvmeNamespace *ns; + NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; + uint32_t min_nsid =3D le32_to_cpu(c->nsid); + uint8_t list[NVME_IDENTIFY_DATA_SIZE] =3D {}; + static const int data_len =3D sizeof(list); + uint32_t *list_ptr =3D (uint32_t *)list; + int i, j =3D 0; + + trace_pci_nvme_identify_nslist_csi(min_nsid, c->csi); + + if (c->csi !=3D NVME_CSI_NVM) { + return NVME_INVALID_FIELD | NVME_DNR; + } + + for (i =3D 1; i <=3D n->num_namespaces; i++) { + ns =3D nvme_ns(n, i); + if (!ns) { + continue; + } + if (ns->params.nsid < min_nsid) { + continue; + } + list_ptr[j++] =3D cpu_to_le32(ns->params.nsid); + if (j =3D=3D data_len / sizeof(uint32_t)) { + break; + } + } + + return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req); } =20 static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req) { NvmeIdentify *c =3D (NvmeIdentify *)&req->cmd; + NvmeNamespace *ns; uint32_t nsid =3D le32_to_cpu(c->nsid); - uint8_t list[NVME_IDENTIFY_DATA_SIZE]; - - struct data { - struct { - NvmeIdNsDescr hdr; - uint8_t v[16]; - } uuid; - }; - - struct data *ns_descrs =3D (struct data *)list; + NvmeIdNsDescr *desc; + uint8_t list[NVME_IDENTIFY_DATA_SIZE] =3D {}; + static const int data_len =3D sizeof(list); + void *list_ptr =3D list; =20 trace_pci_nvme_identify_ns_descr_list(nsid); =20 - if (!nvme_nsid_valid(n, nsid) || nsid =3D=3D NVME_NSID_BROADCAST) { - return NVME_INVALID_NSID | NVME_DNR; - } - if (unlikely(!nvme_ns(n, nsid))) { return NVME_INVALID_FIELD | NVME_DNR; } =20 - memset(list, 0x0, sizeof(list)); + ns =3D nvme_ns(n, nsid); + if (unlikely(!ns)) { + return nvme_rpt_empty_id_struct(n, req); + } =20 /* * Because the NGUID and EUI64 fields are 0 in the Identify Namespace = data @@ -1597,12 +1667,31 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtr= l *n, NvmeRequest *req) * Namespace Identification Descriptor. Add a very basic Namespace UUID * here. */ - ns_descrs->uuid.hdr.nidt =3D NVME_NIDT_UUID; - ns_descrs->uuid.hdr.nidl =3D NVME_NIDL_UUID; - stl_be_p(&ns_descrs->uuid.v, nsid); + desc =3D list_ptr; + desc->nidt =3D NVME_NIDT_UUID; + desc->nidl =3D NVME_NIDL_UUID; + list_ptr +=3D sizeof(*desc); + memcpy(list_ptr, ns->params.uuid.data, NVME_NIDL_UUID); + list_ptr +=3D NVME_NIDL_UUID; =20 - return nvme_dma(n, list, NVME_IDENTIFY_DATA_SIZE, - DMA_DIRECTION_FROM_DEVICE, req); + desc =3D list_ptr; + desc->nidt =3D NVME_NIDT_CSI; + desc->nidl =3D NVME_NIDL_CSI; + list_ptr +=3D sizeof(*desc); + *(uint8_t *)list_ptr =3D NVME_CSI_NVM; + + return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req); +} + +static uint16_t nvme_identify_cmd_set(NvmeCtrl *n, NvmeRequest *req) +{ + uint8_t list[NVME_IDENTIFY_DATA_SIZE] =3D {}; + static const int data_len =3D sizeof(list); + + trace_pci_nvme_identify_cmd_set(); + + NVME_SET_CSI(*list, NVME_CSI_NVM); + return nvme_dma(n, list, data_len, DMA_DIRECTION_FROM_DEVICE, req); } =20 static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequest *req) @@ -1612,12 +1701,20 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeRequ= est *req) switch (le32_to_cpu(c->cns)) { case NVME_ID_CNS_NS: return nvme_identify_ns(n, req); + case NVME_ID_CNS_CS_NS: + return nvme_identify_ns_csi(n, req); case NVME_ID_CNS_CTRL: return nvme_identify_ctrl(n, req); + case NVME_ID_CNS_CS_CTRL: + return nvme_identify_ctrl_csi(n, req); case NVME_ID_CNS_NS_ACTIVE_LIST: return nvme_identify_nslist(n, req); + case NVME_ID_CNS_CS_NS_ACTIVE_LIST: + return nvme_identify_nslist_csi(n, req); case NVME_ID_CNS_NS_DESCR_LIST: return nvme_identify_ns_descr_list(n, req); + case NVME_ID_CNS_IO_COMMAND_SET: + return nvme_identify_cmd_set(n, req); default: trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); return NVME_INVALID_FIELD | NVME_DNR; @@ -1799,6 +1896,9 @@ defaults: result |=3D NVME_INTVC_NOCOALESCING; } =20 + break; + case NVME_COMMAND_SET_PROFILE: + result =3D 0; break; default: result =3D nvme_feature_default[fid]; @@ -1939,6 +2039,12 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRe= quest *req) break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, req); + case NVME_COMMAND_SET_PROFILE: + if (dw11 & 0x1ff) { + trace_pci_nvme_err_invalid_iocsci(dw11 & 0x1ff); + return NVME_CMD_SET_CMB_REJECTED | NVME_DNR; + } + break; default: return NVME_FEAT_NOT_CHANGEABLE | NVME_DNR; } @@ -2222,6 +2328,30 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offse= t, uint64_t data, break; case 0x14: /* CC */ trace_pci_nvme_mmio_cfg(data & 0xffffffff); + + if (NVME_CC_CSS(data) !=3D NVME_CC_CSS(n->bar.cc)) { + if (NVME_CC_EN(n->bar.cc)) { + NVME_GUEST_ERR(pci_nvme_err_change_css_when_enabled, + "changing selected command set when enabled= "); + } else { + switch (NVME_CC_CSS(data)) { + case CSS_NVM_ONLY: + trace_pci_nvme_css_nvm_cset_selected_by_host(data & + 0xfffffff= f); + break; + case CSS_CSI: + NVME_SET_CC_CSS(n->bar.cc, CSS_CSI); + trace_pci_nvme_css_all_csets_sel_by_host(data & 0xffff= ffff); + break; + case CSS_ADMIN_ONLY: + break; + default: + NVME_GUEST_ERR(pci_nvme_ub_unknown_css_value, + "unknown value in CC.CSS field"); + } + } + } + /* Windows first sends data, then sends enable bit */ if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) && !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc)) @@ -2810,7 +2940,11 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *p= ci_dev) NVME_CAP_SET_MQES(n->bar.cap, 0x7ff); NVME_CAP_SET_CQR(n->bar.cap, 1); NVME_CAP_SET_TO(n->bar.cap, 0xf); - NVME_CAP_SET_CSS(n->bar.cap, 1); + /* + * The device now always supports NS Types, but all commands + * that support CSI field will only handle NVM Command Set. + */ + NVME_CAP_SET_CSS(n->bar.cap, (CAP_CSS_NVM | CAP_CSS_CSI_SUPP)); NVME_CAP_SET_MPSMAX(n->bar.cap, 4); =20 n->bar.vs =3D NVME_SPEC_VER; --=20 2.21.0