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charset="utf-8" Signed-off-by: Luc Michel Reviewed-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/clock.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/hw/clock.h b/include/hw/clock.h index d357594df9..c93e6113cd 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -79,10 +79,15 @@ struct Clock { extern const VMStateDescription vmstate_clock; #define VMSTATE_CLOCK(field, state) \ VMSTATE_CLOCK_V(field, state, 0) #define VMSTATE_CLOCK_V(field, state, version) \ VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock) +#define VMSTATE_ARRAY_CLOCK(field, state, num) \ + VMSTATE_ARRAY_CLOCK_V(field, state, num, 0) +#define VMSTATE_ARRAY_CLOCK_V(field, state, num, version) \ + VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(field, state, num, version, \ + vmstate_clock, Clock) =20 /** * clock_setup_canonical_path: * @clk: clock * --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" The nanosecond unit greatly limits the dynamic range we can display in clock value traces, for values in the order of 1GHz and more. The internal representation can go way beyond this value and it is quite common for today's clocks to be within those ranges. For example, a frequency between 500MHz+ and 1GHz will be displayed as 1ns. Beyond 1GHz, it will show up as 0ns. Replace nanosecond periods traces with frequencies in the Hz unit to have more dynamic range in the trace output. Signed-off-by: Luc Michel Reviewed-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/core/clock.c | 6 +++--- hw/core/trace-events | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/core/clock.c b/hw/core/clock.c index 7066282f7b..81184734e0 100644 --- a/hw/core/clock.c +++ b/hw/core/clock.c @@ -37,12 +37,12 @@ void clock_clear_callback(Clock *clk) bool clock_set(Clock *clk, uint64_t period) { if (clk->period =3D=3D period) { return false; } - trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period), - CLOCK_PERIOD_TO_NS(period)); + trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_HZ(clk->period), + CLOCK_PERIOD_TO_HZ(period)); clk->period =3D period; =20 return true; } =20 @@ -52,11 +52,11 @@ static void clock_propagate_period(Clock *clk, bool cal= l_callbacks) =20 QLIST_FOREACH(child, &clk->children, sibling) { if (child->period !=3D clk->period) { child->period =3D clk->period; trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), - CLOCK_PERIOD_TO_NS(clk->period), + CLOCK_PERIOD_TO_HZ(clk->period), call_callbacks); if (call_callbacks && child->callback) { child->callback(child->callback_opaque); } clock_propagate_period(child, call_callbacks); diff --git a/hw/core/trace-events b/hw/core/trace-events index 1ac60ede6b..6f96d8bfd0 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -29,8 +29,8 @@ resettable_phase_exit_end(void *obj, const char *objtype,= unsigned count) "obj=3D% resettable_transitional_function(void *obj, const char *objtype) "obj=3D%p= (%s)" =20 # clock.c clock_set_source(const char *clk, const char *src) "'%s', src=3D'%s'" clock_disconnect(const char *clk) "'%s'" -clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=3D%"PRIu6= 4"->%"PRIu64 +clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', %"PRIu64"hz-= >%"PRIu64"hz" clock_propagate(const char *clk) "'%s'" -clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s'= , src=3D'%s', ns=3D%"PRIu64", cb=3D%d" +clock_update(const char *clk, const char *src, uint64_t hz, int cb) "'%s',= src=3D'%s', val=3D%"PRIu64"hz cb=3D%d" --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The cprman (clock controller) was mapped at the watchdog/power manager address. It was also split into two unimplemented peripherals (cm and a2w) but this is really the same one, as shown by this extract of the Raspberry Pi 3 Linux device tree: watchdog@7e100000 { compatible =3D "brcm,bcm2835-pm\0brcm,bcm2835-pm-wdt"; [...] reg =3D <0x7e100000 0x114 0x7e00a000 0x24>; [...] }; [...] cprman@7e101000 { compatible =3D "brcm,bcm2835-cprman"; [...] reg =3D <0x7e101000 0x2000>; [...] }; Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/bcm2835_peripherals.h | 2 +- include/hw/arm/raspi_platform.h | 5 ++--- hw/arm/bcm2835_peripherals.c | 4 ++-- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index 13d7c4c553..199088425a 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -44,12 +44,12 @@ struct BCM2835PeripheralState { qemu_irq irq, fiq; =20 BCM2835SystemTimerState systmr; BCM2835MphiState mphi; UnimplementedDeviceState armtmr; + UnimplementedDeviceState powermgt; UnimplementedDeviceState cprman; - UnimplementedDeviceState a2w; PL011State uart0; BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; BCM2835ICState ic; diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platfor= m.h index 61b04a1bd4..51a477cdc2 100644 --- a/include/hw/arm/raspi_platform.h +++ b/include/hw/arm/raspi_platform.h @@ -34,13 +34,12 @@ #define ARMCTRL_OFFSET (ARM_OFFSET + 0x000) #define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controll= er */ #define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */ #define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semap= hores * Doorbells & Mailbo= xes */ -#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */ -#define CM_OFFSET 0x101000 /* Clock Management */ -#define A2W_OFFSET 0x102000 /* Reset controller */ +#define PM_OFFSET 0x100000 /* Power Management */ +#define CPRMAN_OFFSET 0x101000 /* Clock Management */ #define AVS_OFFSET 0x103000 /* Audio Video Standard */ #define RNG_OFFSET 0x104000 #define GPIO_OFFSET 0x200000 #define UART0_OFFSET 0x201000 #define MMCI0_OFFSET 0x202000 diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index a9d7f53f6e..f0802c91e0 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -342,12 +342,12 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0, qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_USB)); =20 create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, = 0x40); - create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); - create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); + create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); + create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x2000); create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20); --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1601029284027929.8090975061292; Fri, 25 Sep 2020 03:21:24 -0700 (PDT) Received: from localhost ([::1]:54380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kLkqw-00063q-M2 for importer@patchew.org; Fri, 25 Sep 2020 06:21:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42668) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknE-00014C-VN; Fri, 25 Sep 2020 06:17:32 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58100) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLkn8-0007QL-AP; Fri, 25 Sep 2020 06:17:32 -0400 Received: from sekoia-pc.bar.greensocs.com (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id 28283C60F1C; Fri, 25 Sep 2020 10:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=raXzaOuCKS7gHcT4Y4vqhXTILWOECsdtqSASUoQ9XTo=; b=Kevn0f3jRLKSH2PEfU7ND7apEpK3HEk/3sQx3/+cKTy/JtpH/e5uXKfUWaJp4AMaqV3SQY hF8Vz4VP8me8LCTPLOm95xxmgIBFq+nndlJtmwXqpaTNbgVSHVkBnnYZzj29M0ZAcnsUsY fYTXNPYFmEE0eQXgfnyggnQfPNTwwVmvchbsTRChVbPoN2phkMqMLjhyPjUd2Ku9R3axb1 oNqIK7A71RDTahEpsjNYgI+MkLonKptWqOCOHkl3aifXMzMMzn2PRQfesbdMl9+27TRZz8 WoxleXrbCXQzI3Z4DVTqtCzIp2cpnXtR/weJOi0BK2WkP7LkCQlm+b4AFNhIlw== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 04/14] hw/arm/raspi: add a skeleton implementation of the cprman Date: Fri, 25 Sep 2020 12:17:21 +0200 Message-Id: <20200925101731.2159827-5-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; 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helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The BCM2835 cprman is the clock manager of the SoC. It is composed of a main oscillator, and several sub-components (PLLs, multiplexers, ...) to generate the BCM2835 clock tree. This commit adds a skeleton of the cprman, with a dummy register read/write implementation. It embeds the main oscillator (xosc) from which all the clocks will be derived. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/arm/bcm2835_peripherals.h | 3 +- include/hw/misc/bcm2835_cprman.h | 37 +++++ include/hw/misc/bcm2835_cprman_internals.h | 24 +++ hw/arm/bcm2835_peripherals.c | 11 +- hw/misc/bcm2835_cprman.c | 171 +++++++++++++++++++++ hw/misc/meson.build | 1 + hw/misc/trace-events | 5 + 7 files changed, 250 insertions(+), 2 deletions(-) create mode 100644 include/hw/misc/bcm2835_cprman.h create mode 100644 include/hw/misc/bcm2835_cprman_internals.h create mode 100644 hw/misc/bcm2835_cprman.c diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index 199088425a..002bb5e73b 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -21,10 +21,11 @@ #include "hw/misc/bcm2835_property.h" #include "hw/misc/bcm2835_rng.h" #include "hw/misc/bcm2835_mbox.h" #include "hw/misc/bcm2835_mphi.h" #include "hw/misc/bcm2835_thermal.h" +#include "hw/misc/bcm2835_cprman.h" #include "hw/sd/sdhci.h" #include "hw/sd/bcm2835_sdhost.h" #include "hw/gpio/bcm2835_gpio.h" #include "hw/timer/bcm2835_systmr.h" #include "hw/usb/hcd-dwc2.h" @@ -45,11 +46,11 @@ struct BCM2835PeripheralState { =20 BCM2835SystemTimerState systmr; BCM2835MphiState mphi; UnimplementedDeviceState armtmr; UnimplementedDeviceState powermgt; - UnimplementedDeviceState cprman; + BCM2835CprmanState cprman; PL011State uart0; BCM2835AuxState aux; BCM2835FBState fb; BCM2835DMAState dma; BCM2835ICState ic; diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr= man.h new file mode 100644 index 0000000000..de9bd01b23 --- /dev/null +++ b/include/hw/misc/bcm2835_cprman.h @@ -0,0 +1,37 @@ +/* + * BCM2835 cprman clock manager + * + * Copyright (c) 2020 Luc Michel + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_CPRMAN_H +#define HW_MISC_CPRMAN_H + +#include "hw/sysbus.h" +#include "hw/qdev-clock.h" + +#define TYPE_BCM2835_CPRMAN "bcm2835-cprman" + +typedef struct BCM2835CprmanState BCM2835CprmanState; + +DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN, + TYPE_BCM2835_CPRMAN) + +#define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t)) + +struct BCM2835CprmanState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion iomem; + + uint32_t regs[CPRMAN_NUM_REGS]; + uint32_t xosc_freq; + + Clock *xosc; +}; + +#endif diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h new file mode 100644 index 0000000000..6a10b60930 --- /dev/null +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -0,0 +1,24 @@ +/* + * BCM2835 cprman clock manager + * + * Copyright (c) 2020 Luc Michel + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_MISC_CPRMAN_INTERNALS_H +#define HW_MISC_CPRMAN_INTERNALS_H + +#include "hw/registerfields.h" +#include "hw/misc/bcm2835_cprman.h" + +/* Register map */ + +/* + * This field is common to all registers. Each register write value must m= atch + * the CPRMAN_PASSWORD magic value in its 8 MSB. + */ +FIELD(CPRMAN, PASSWORD, 24, 8) +#define CPRMAN_PASSWORD 0x5a + +#endif diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index f0802c91e0..958aadeeb9 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -119,10 +119,13 @@ static void bcm2835_peripherals_init(Object *obj) object_initialize_child(obj, "mphi", &s->mphi, TYPE_BCM2835_MPHI); =20 /* DWC2 */ object_initialize_child(obj, "dwc2", &s->dwc2, TYPE_DWC2_USB); =20 + /* CPRMAN clock manager */ + object_initialize_child(obj, "cprman", &s->cprman, TYPE_BCM2835_CPRMAN= ); + object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", OBJECT(&s->gpu_bus_mr)); } =20 static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp) @@ -158,10 +161,17 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) /* Interrupt Controller */ if (!sysbus_realize(SYS_BUS_DEVICE(&s->ic), errp)) { return; } =20 + /* CPRMAN clock manager */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) { + return; + } + memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); + memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); =20 /* Sys Timer */ @@ -343,11 +353,10 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_USB)); =20 create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, = 0x40); create_unimp(s, &s->powermgt, "bcm2835-powermgt", PM_OFFSET, 0x114); - create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x2000); create_unimp(s, &s->i2s, "bcm2835-i2s", I2S_OFFSET, 0x100); create_unimp(s, &s->smi, "bcm2835-smi", SMI_OFFSET, 0x100); create_unimp(s, &s->spi[0], "bcm2835-spi0", SPI0_OFFSET, 0x20); create_unimp(s, &s->bscsl, "bcm2835-spis", BSC_SL_OFFSET, 0x100); create_unimp(s, &s->i2c[0], "bcm2835-i2c0", BSC0_OFFSET, 0x20); diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c new file mode 100644 index 0000000000..d2ea0c9236 --- /dev/null +++ b/hw/misc/bcm2835_cprman.c @@ -0,0 +1,171 @@ +/* + * BCM2835 cprman clock manager + * + * Copyright (c) 2020 Luc Michel + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +/* + * This peripheral is roughly divided into 3 main parts: + * - the PLLs + * - the PLL channels + * - the clock muxes + * + * A main oscillator (xosc) feeds all the PLLs. Each PLLs has one or more + * channels. Those channel are then connected to the clock muxes. Each mux= has + * multiples sources (usually the xosc, some of the PLL channels and some = "test + * debug" clocks). It can selects one or the other through a control regis= ter. + * Each mux has one output clock that also goes out of the CPRMAN. It usua= lly + * connects to another peripheral in the SoC (so a given mux is dedicated = to a + * peripheral). + * + * At each level (PLL, channel and mux), the clock can be altered through + * dividers (and multipliers in case of the PLLs), and can be disabled (in= this + * case, the next levels see no clock). + * + * This can be sum-up as follows (this is an example and not the actual BC= M2835 + * clock tree): + * + * /-->[PLL]-|->[PLL channel]--... [mux]--> to periphe= rals + * | |->[PLL channel] muxes takes [mux] + * | \->[PLL channel] inputs from [mux] + * | some channels [mux] + * [xosc]---|-->[PLL]-|->[PLL channel] and other srcs [mux] + * | \->[PLL channel] ...-->[mux] + * | [mux] + * \-->[PLL]--->[PLL channel] [mux] + * + * The page at https://elinux.org/The_Undocumented_Pi gives the actual clo= ck + * tree configuration. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/misc/bcm2835_cprman.h" +#include "hw/misc/bcm2835_cprman_internals.h" +#include "trace.h" + +/* CPRMAN "top level" model */ + +static uint64_t cprman_read(void *opaque, hwaddr offset, + unsigned size) +{ + BCM2835CprmanState *s =3D CPRMAN(opaque); + uint64_t r =3D 0; + size_t idx =3D offset / sizeof(uint32_t); + + switch (idx) { + default: + r =3D s->regs[idx]; + } + + trace_bcm2835_cprman_read(offset, r); + return r; +} + +static void cprman_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + BCM2835CprmanState *s =3D CPRMAN(opaque); + size_t idx =3D offset / sizeof(uint32_t); + + if (FIELD_EX32(value, CPRMAN, PASSWORD) !=3D CPRMAN_PASSWORD) { + trace_bcm2835_cprman_write_invalid_magic(offset, value); + return; + } + + value &=3D ~R_CPRMAN_PASSWORD_MASK; + + trace_bcm2835_cprman_write(offset, value); + s->regs[idx] =3D value; + +} + +static const MemoryRegionOps cprman_ops =3D { + .read =3D cprman_read, + .write =3D cprman_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + .unaligned =3D false, + }, +}; + +static void cprman_reset(DeviceState *dev) +{ + BCM2835CprmanState *s =3D CPRMAN(dev); + + memset(s->regs, 0, sizeof(s->regs)); + + clock_update_hz(s->xosc, s->xosc_freq); +} + +static Clock *init_internal_clock(BCM2835CprmanState *s, + const char *name) +{ + Object *obj; + Clock *clk; + + obj =3D object_new(TYPE_CLOCK); + object_property_add_child(OBJECT(s), name, obj); + object_unref(obj); + + clk =3D CLOCK(obj); + clock_setup_canonical_path(clk); + + return clk; +} + +static void cprman_init(Object *obj) +{ + BCM2835CprmanState *s =3D CPRMAN(obj); + + s->xosc =3D init_internal_clock(s, "xosc"); + + memory_region_init_io(&s->iomem, obj, &cprman_ops, + s, "bcm2835-cprman", 0x2000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); +} + +static const VMStateDescription cprman_vmstate =3D { + .name =3D TYPE_BCM2835_CPRMAN, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, BCM2835CprmanState, CPRMAN_NUM_REGS), + VMSTATE_END_OF_LIST() + } +}; + +static Property cprman_properties[] =3D { + DEFINE_PROP_UINT32("xosc-freq", BCM2835CprmanState, xosc_freq, 1920000= 0), + DEFINE_PROP_END_OF_LIST() +}; + +static void cprman_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D cprman_reset; + dc->vmsd =3D &cprman_vmstate; + device_class_set_props(dc, cprman_properties); +} + +static const TypeInfo cprman_info =3D { + .name =3D TYPE_BCM2835_CPRMAN, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BCM2835CprmanState), + .class_init =3D cprman_class_init, + .instance_init =3D cprman_init, +}; + +static void cprman_register_types(void) +{ + type_register_static(&cprman_info); +} + +type_init(cprman_register_types); diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 793d45b1dc..c94cf70e82 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -71,10 +71,11 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files( 'bcm2835_mbox.c', 'bcm2835_mphi.c', 'bcm2835_property.c', 'bcm2835_rng.c', 'bcm2835_thermal.c', + 'bcm2835_cprman.c', )) softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c', 'zynq-xa= dc.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_SYSCFG', if_true: files('stm32f2xx_= syscfg.c')) softmmu_ss.add(when: 'CONFIG_STM32F4XX_SYSCFG', if_true: files('stm32f4xx_= syscfg.c')) diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 6054f9adf3..d718a2b177 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -224,5 +224,10 @@ grlib_ahb_pnp_read(uint64_t addr, uint32_t value) "AHB= PnP read addr:0x%03"PRIx6 grlib_apb_pnp_read(uint64_t addr, uint32_t value) "APB PnP read addr:0x%03= "PRIx64" data:0x%08x" =20 # pca9552.c pca955x_gpio_status(const char *description, const char *buf) "%s GPIOs 0-= 15 [%s]" pca955x_gpio_change(const char *description, unsigned id, unsigned prev_st= ate, unsigned current_state) "%s GPIO id:%u status: %u -> %u" + +# bcm2835_cprman.c +bcm2835_cprman_read(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 "= value:0x%" PRIx64 +bcm2835_cprman_write(uint64_t offset, uint64_t value) "offset:0x%" PRIx64 = " value:0x%" PRIx64 +bcm2835_cprman_write_invalid_magic(uint64_t offset, uint64_t value) "offse= t:0x%" PRIx64 " value:0x%" PRIx64 --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" There is 5 PLLs in the cprman, namely PLL A, C, D, H and B. All of them take the xosc clock as input and produce a new clock. This commit adds a skeleton implementation for the PLLs as sub-devices of the cprman. The PLLs are instantiated and connected internally to the main oscillator. Each PLL has 6 registers : cm, a2w_ctrl, a2w_ana[0,1,2,3], a2w_frac. A write to any of them triggers a call to the (not yet implemented) pll_update function. If the main oscillator changes frequency, an update is also triggered. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/bcm2835_cprman.h | 29 +++++ include/hw/misc/bcm2835_cprman_internals.h | 144 +++++++++++++++++++++ hw/misc/bcm2835_cprman.c | 108 ++++++++++++++++ 3 files changed, 281 insertions(+) diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr= man.h index de9bd01b23..f186ab0104 100644 --- a/include/hw/misc/bcm2835_cprman.h +++ b/include/hw/misc/bcm2835_cprman.h @@ -19,17 +19,46 @@ typedef struct BCM2835CprmanState BCM2835CprmanState; DECLARE_INSTANCE_CHECKER(BCM2835CprmanState, CPRMAN, TYPE_BCM2835_CPRMAN) =20 #define CPRMAN_NUM_REGS (0x2000 / sizeof(uint32_t)) =20 +typedef enum CprmanPLL { + CPRMAN_PLLA =3D 0, + CPRMAN_PLLC, + CPRMAN_PLLD, + CPRMAN_PLLH, + CPRMAN_PLLB, + + CPRMAN_NUM_PLL +} CprmanPLL; + +typedef struct CprmanPLLState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CprmanPLL id; + + uint32_t *reg_cm; + uint32_t *reg_a2w_ctrl; + uint32_t *reg_a2w_ana; + uint32_t prediv_mask; /* prediv bit in ana[1] */ + uint32_t *reg_a2w_frac; + + Clock *xosc_in; + Clock *out; +} CprmanPLLState; + struct BCM2835CprmanState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; =20 + CprmanPLLState plls[CPRMAN_NUM_PLL]; + uint32_t regs[CPRMAN_NUM_REGS]; uint32_t xosc_freq; =20 Clock *xosc; }; diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index 6a10b60930..5cfa849492 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -10,15 +10,159 @@ #define HW_MISC_CPRMAN_INTERNALS_H =20 #include "hw/registerfields.h" #include "hw/misc/bcm2835_cprman.h" =20 +#define TYPE_CPRMAN_PLL "bcm2835-cprman-pll" + +DECLARE_INSTANCE_CHECKER(CprmanPLLState, CPRMAN_PLL, + TYPE_CPRMAN_PLL) + /* Register map */ =20 +/* PLLs */ +REG32(CM_PLLA, 0x104) + FIELD(CM_PLLA, LOADDSI0, 0, 1) + FIELD(CM_PLLA, HOLDDSI0, 1, 1) + FIELD(CM_PLLA, LOADCCP2, 2, 1) + FIELD(CM_PLLA, HOLDCCP2, 3, 1) + FIELD(CM_PLLA, LOADCORE, 4, 1) + FIELD(CM_PLLA, HOLDCORE, 5, 1) + FIELD(CM_PLLA, LOADPER, 6, 1) + FIELD(CM_PLLA, HOLDPER, 7, 1) + FIELD(CM_PLLx, ANARST, 8, 1) +REG32(CM_PLLC, 0x108) + FIELD(CM_PLLC, LOADCORE0, 0, 1) + FIELD(CM_PLLC, HOLDCORE0, 1, 1) + FIELD(CM_PLLC, LOADCORE1, 2, 1) + FIELD(CM_PLLC, HOLDCORE1, 3, 1) + FIELD(CM_PLLC, LOADCORE2, 4, 1) + FIELD(CM_PLLC, HOLDCORE2, 5, 1) + FIELD(CM_PLLC, LOADPER, 6, 1) + FIELD(CM_PLLC, HOLDPER, 7, 1) +REG32(CM_PLLD, 0x10c) + FIELD(CM_PLLD, LOADDSI0, 0, 1) + FIELD(CM_PLLD, HOLDDSI0, 1, 1) + FIELD(CM_PLLD, LOADDSI1, 2, 1) + FIELD(CM_PLLD, HOLDDSI1, 3, 1) + FIELD(CM_PLLD, LOADCORE, 4, 1) + FIELD(CM_PLLD, HOLDCORE, 5, 1) + FIELD(CM_PLLD, LOADPER, 6, 1) + FIELD(CM_PLLD, HOLDPER, 7, 1) +REG32(CM_PLLH, 0x110) + FIELD(CM_PLLH, LOADPIX, 0, 1) + FIELD(CM_PLLH, LOADAUX, 1, 1) + FIELD(CM_PLLH, LOADRCAL, 2, 1) +REG32(CM_PLLB, 0x170) + FIELD(CM_PLLB, LOADARM, 0, 1) + FIELD(CM_PLLB, HOLDARM, 1, 1) + +REG32(A2W_PLLA_CTRL, 0x1100) + FIELD(A2W_PLLx_CTRL, NDIV, 0, 10) + FIELD(A2W_PLLx_CTRL, PDIV, 12, 3) + FIELD(A2W_PLLx_CTRL, PWRDN, 16, 1) + FIELD(A2W_PLLx_CTRL, PRST_DISABLE, 17, 1) +REG32(A2W_PLLC_CTRL, 0x1120) +REG32(A2W_PLLD_CTRL, 0x1140) +REG32(A2W_PLLH_CTRL, 0x1160) +REG32(A2W_PLLB_CTRL, 0x11e0) + +REG32(A2W_PLLA_ANA0, 0x1010) +REG32(A2W_PLLA_ANA1, 0x1014) + FIELD(A2W_PLLx_ANA1, FB_PREDIV, 14, 1) +REG32(A2W_PLLA_ANA2, 0x1018) +REG32(A2W_PLLA_ANA3, 0x101c) + +REG32(A2W_PLLC_ANA0, 0x1030) +REG32(A2W_PLLC_ANA1, 0x1034) +REG32(A2W_PLLC_ANA2, 0x1038) +REG32(A2W_PLLC_ANA3, 0x103c) + +REG32(A2W_PLLD_ANA0, 0x1050) +REG32(A2W_PLLD_ANA1, 0x1054) +REG32(A2W_PLLD_ANA2, 0x1058) +REG32(A2W_PLLD_ANA3, 0x105c) + +REG32(A2W_PLLH_ANA0, 0x1070) +REG32(A2W_PLLH_ANA1, 0x1074) + FIELD(A2W_PLLH_ANA1, FB_PREDIV, 11, 1) +REG32(A2W_PLLH_ANA2, 0x1078) +REG32(A2W_PLLH_ANA3, 0x107c) + +REG32(A2W_PLLB_ANA0, 0x10f0) +REG32(A2W_PLLB_ANA1, 0x10f4) +REG32(A2W_PLLB_ANA2, 0x10f8) +REG32(A2W_PLLB_ANA3, 0x10fc) + +REG32(A2W_PLLA_FRAC, 0x1200) + FIELD(A2W_PLLx_FRAC, FRAC, 0, 20) +REG32(A2W_PLLC_FRAC, 0x1220) +REG32(A2W_PLLD_FRAC, 0x1240) +REG32(A2W_PLLH_FRAC, 0x1260) +REG32(A2W_PLLB_FRAC, 0x12e0) + /* * This field is common to all registers. Each register write value must m= atch * the CPRMAN_PASSWORD magic value in its 8 MSB. */ FIELD(CPRMAN, PASSWORD, 24, 8) #define CPRMAN_PASSWORD 0x5a =20 +/* PLL init info */ +typedef struct PLLInitInfo { + const char *name; + size_t cm_offset; + size_t a2w_ctrl_offset; + size_t a2w_ana_offset; + uint32_t prediv_mask; /* Prediv bit in ana[1] */ + size_t a2w_frac_offset; +} PLLInitInfo; + +#define FILL_PLL_INIT_INFO(pll_) \ + .cm_offset =3D R_CM_ ## pll_, \ + .a2w_ctrl_offset =3D R_A2W_ ## pll_ ## _CTRL, \ + .a2w_ana_offset =3D R_A2W_ ## pll_ ## _ANA0, \ + .a2w_frac_offset =3D R_A2W_ ## pll_ ## _FRAC + +static const PLLInitInfo PLL_INIT_INFO[] =3D { + [CPRMAN_PLLA] =3D { + .name =3D "plla", + .prediv_mask =3D R_A2W_PLLx_ANA1_FB_PREDIV_MASK, + FILL_PLL_INIT_INFO(PLLA), + }, + [CPRMAN_PLLC] =3D { + .name =3D "pllc", + .prediv_mask =3D R_A2W_PLLx_ANA1_FB_PREDIV_MASK, + FILL_PLL_INIT_INFO(PLLC), + }, + [CPRMAN_PLLD] =3D { + .name =3D "plld", + .prediv_mask =3D R_A2W_PLLx_ANA1_FB_PREDIV_MASK, + FILL_PLL_INIT_INFO(PLLD), + }, + [CPRMAN_PLLH] =3D { + .name =3D "pllh", + .prediv_mask =3D R_A2W_PLLH_ANA1_FB_PREDIV_MASK, + FILL_PLL_INIT_INFO(PLLH), + }, + [CPRMAN_PLLB] =3D { + .name =3D "pllb", + .prediv_mask =3D R_A2W_PLLx_ANA1_FB_PREDIV_MASK, + FILL_PLL_INIT_INFO(PLLB), + }, +}; + +#undef FILL_PLL_CHANNEL_INIT_INFO + +static inline void set_pll_init_info(BCM2835CprmanState *s, + CprmanPLLState *pll, + CprmanPLL id) +{ + pll->id =3D id; + pll->reg_cm =3D &s->regs[PLL_INIT_INFO[id].cm_offset]; + pll->reg_a2w_ctrl =3D &s->regs[PLL_INIT_INFO[id].a2w_ctrl_offset]; + pll->reg_a2w_ana =3D &s->regs[PLL_INIT_INFO[id].a2w_ana_offset]; + pll->prediv_mask =3D PLL_INIT_INFO[id].prediv_mask; + pll->reg_a2w_frac =3D &s->regs[PLL_INIT_INFO[id].a2w_frac_offset]; +} + #endif diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index d2ea0c9236..ad71d30a86 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -46,10 +46,56 @@ #include "hw/qdev-properties.h" #include "hw/misc/bcm2835_cprman.h" #include "hw/misc/bcm2835_cprman_internals.h" #include "trace.h" =20 +/* PLL */ + +static void pll_update(CprmanPLLState *pll) +{ + clock_update(pll->out, 0); +} + +static void pll_xosc_update(void *opaque) +{ + pll_update(CPRMAN_PLL(opaque)); +} + +static void pll_init(Object *obj) +{ + CprmanPLLState *s =3D CPRMAN_PLL(obj); + + s->xosc_in =3D qdev_init_clock_in(DEVICE(s), "xosc-in", pll_xosc_updat= e, s); + s->out =3D qdev_init_clock_out(DEVICE(s), "out"); +} + +static const VMStateDescription pll_vmstate =3D { + .name =3D TYPE_CPRMAN_PLL, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(xosc_in, CprmanPLLState), + VMSTATE_END_OF_LIST() + } +}; + +static void pll_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &pll_vmstate; +} + +static const TypeInfo cprman_pll_info =3D { + .name =3D TYPE_CPRMAN_PLL, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CprmanPLLState), + .class_init =3D pll_class_init, + .instance_init =3D pll_init, +}; + + /* CPRMAN "top level" model */ =20 static uint64_t cprman_read(void *opaque, hwaddr offset, unsigned size) { @@ -64,10 +110,19 @@ static uint64_t cprman_read(void *opaque, hwaddr offse= t, =20 trace_bcm2835_cprman_read(offset, r); return r; } =20 +#define CASE_PLL_REGS(pll_) \ + case R_CM_ ## pll_: \ + case R_A2W_ ## pll_ ## _CTRL: \ + case R_A2W_ ## pll_ ## _ANA0: \ + case R_A2W_ ## pll_ ## _ANA1: \ + case R_A2W_ ## pll_ ## _ANA2: \ + case R_A2W_ ## pll_ ## _ANA3: \ + case R_A2W_ ## pll_ ## _FRAC + static void cprman_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { BCM2835CprmanState *s =3D CPRMAN(opaque); size_t idx =3D offset / sizeof(uint32_t); @@ -80,12 +135,35 @@ static void cprman_write(void *opaque, hwaddr offset, value &=3D ~R_CPRMAN_PASSWORD_MASK; =20 trace_bcm2835_cprman_write(offset, value); s->regs[idx] =3D value; =20 + switch (idx) { + CASE_PLL_REGS(PLLA) : + pll_update(&s->plls[CPRMAN_PLLA]); + break; + + CASE_PLL_REGS(PLLC) : + pll_update(&s->plls[CPRMAN_PLLC]); + break; + + CASE_PLL_REGS(PLLD) : + pll_update(&s->plls[CPRMAN_PLLD]); + break; + + CASE_PLL_REGS(PLLH) : + pll_update(&s->plls[CPRMAN_PLLH]); + break; + + CASE_PLL_REGS(PLLB) : + pll_update(&s->plls[CPRMAN_PLLB]); + break; + } } =20 +#undef CASE_PLL_REGS + static const MemoryRegionOps cprman_ops =3D { .read =3D cprman_read, .write =3D cprman_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { @@ -96,13 +174,18 @@ static const MemoryRegionOps cprman_ops =3D { }; =20 static void cprman_reset(DeviceState *dev) { BCM2835CprmanState *s =3D CPRMAN(dev); + size_t i; =20 memset(s->regs, 0, sizeof(s->regs)); =20 + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + device_cold_reset(DEVICE(&s->plls[i])); + } + clock_update_hz(s->xosc, s->xosc_freq); } =20 static Clock *init_internal_clock(BCM2835CprmanState *s, const char *name) @@ -121,18 +204,41 @@ static Clock *init_internal_clock(BCM2835CprmanState = *s, } =20 static void cprman_init(Object *obj) { BCM2835CprmanState *s =3D CPRMAN(obj); + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + object_initialize_child(obj, PLL_INIT_INFO[i].name, + &s->plls[i], TYPE_CPRMAN_PLL); + set_pll_init_info(s, &s->plls[i], i); + } =20 s->xosc =3D init_internal_clock(s, "xosc"); =20 memory_region_init_io(&s->iomem, obj, &cprman_ops, s, "bcm2835-cprman", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); } =20 +static void cprman_realize(DeviceState *dev, Error **errp) +{ + BCM2835CprmanState *s =3D CPRMAN(dev); + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + CprmanPLLState *pll =3D &s->plls[i]; + + clock_set_source(pll->xosc_in, s->xosc); + + if (!qdev_realize(DEVICE(pll), NULL, errp)) { + return; + } + } +} + static const VMStateDescription cprman_vmstate =3D { .name =3D TYPE_BCM2835_CPRMAN, .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { @@ -148,10 +254,11 @@ static Property cprman_properties[] =3D { =20 static void cprman_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->realize =3D cprman_realize; dc->reset =3D cprman_reset; dc->vmsd =3D &cprman_vmstate; device_class_set_props(dc, cprman_properties); } =20 @@ -164,8 +271,9 @@ static const TypeInfo cprman_info =3D { }; =20 static void cprman_register_types(void) { type_register_static(&cprman_info); + type_register_static(&cprman_pll_info); } =20 type_init(cprman_register_types); --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" The cprman PLLs generate a clock based on a prescaler, a multiplier and a divider. The prescaler doubles the parent (xosc) frequency, then the multiplier/divider are applied. The multiplier has an integer and a fractionnal part. This commit also implements the cprman CM_LOCK register. This register reports which PLL is currently locked. We consider a PLL has being locked as soon as it is enabled (on real hardware, there is a delay after turning a PLL on, for it to stabilise). Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/bcm2835_cprman_internals.h | 8 +++ hw/misc/bcm2835_cprman.c | 64 +++++++++++++++++++++- 2 files changed, 71 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index 5cfa849492..22a2500ab0 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -98,10 +98,18 @@ REG32(A2W_PLLA_FRAC, 0x1200) REG32(A2W_PLLC_FRAC, 0x1220) REG32(A2W_PLLD_FRAC, 0x1240) REG32(A2W_PLLH_FRAC, 0x1260) REG32(A2W_PLLB_FRAC, 0x12e0) =20 +/* misc registers */ +REG32(CM_LOCK, 0x114) + FIELD(CM_LOCK, FLOCKH, 12, 1) + FIELD(CM_LOCK, FLOCKD, 11, 1) + FIELD(CM_LOCK, FLOCKC, 10, 1) + FIELD(CM_LOCK, FLOCKB, 9, 1) + FIELD(CM_LOCK, FLOCKA, 8, 1) + /* * This field is common to all registers. Each register write value must m= atch * the CPRMAN_PASSWORD magic value in its 8 MSB. */ FIELD(CPRMAN, PASSWORD, 24, 8) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index ad71d30a86..ba82522eb1 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -48,13 +48,51 @@ #include "hw/misc/bcm2835_cprman_internals.h" #include "trace.h" =20 /* PLL */ =20 +static bool pll_is_locked(const CprmanPLLState *pll) +{ + return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) + && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); +} + static void pll_update(CprmanPLLState *pll) { - clock_update(pll->out, 0); + uint64_t freq, ndiv, fdiv, pdiv; + + if (!pll_is_locked(pll)) { + clock_update(pll->out, 0); + return; + } + + pdiv =3D FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PDIV); + + if (!pdiv) { + clock_update(pll->out, 0); + return; + } + + ndiv =3D FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, NDIV); + fdiv =3D FIELD_EX32(*pll->reg_a2w_frac, A2W_PLLx_FRAC, FRAC); + + if (pll->reg_a2w_ana[1] & pll->prediv_mask) { + /* The prescaler doubles the parent frequency */ + ndiv *=3D 2; + fdiv *=3D 2; + } + + /* + * We have a multiplier with an integer part (ndiv) and a fractional p= art + * (fdiv), and a divider (pdiv). + */ + freq =3D clock_get_hz(pll->xosc_in) * + ((ndiv << R_A2W_PLLx_FRAC_FRAC_LENGTH) + fdiv); + freq /=3D pdiv; + freq >>=3D R_A2W_PLLx_FRAC_FRAC_LENGTH; + + clock_update_hz(pll->out, freq); } =20 static void pll_xosc_update(void *opaque) { pll_update(CPRMAN_PLL(opaque)); @@ -94,18 +132,42 @@ static const TypeInfo cprman_pll_info =3D { }; =20 =20 /* CPRMAN "top level" model */ =20 +static uint32_t get_cm_lock(const BCM2835CprmanState *s) +{ + static const int CM_LOCK_MAPPING[] =3D { + [CPRMAN_PLLA] =3D R_CM_LOCK_FLOCKA_SHIFT, + [CPRMAN_PLLC] =3D R_CM_LOCK_FLOCKC_SHIFT, + [CPRMAN_PLLD] =3D R_CM_LOCK_FLOCKD_SHIFT, + [CPRMAN_PLLH] =3D R_CM_LOCK_FLOCKH_SHIFT, + [CPRMAN_PLLB] =3D R_CM_LOCK_FLOCKB_SHIFT, + }; + + uint32_t r =3D 0; + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + r |=3D pll_is_locked(&s->plls[i]) << CM_LOCK_MAPPING[i]; + } + + return r; +} + static uint64_t cprman_read(void *opaque, hwaddr offset, unsigned size) { BCM2835CprmanState *s =3D CPRMAN(opaque); uint64_t r =3D 0; size_t idx =3D offset / sizeof(uint32_t); =20 switch (idx) { + case R_CM_LOCK: + r =3D get_cm_lock(s); + break; + default: r =3D s->regs[idx]; } =20 trace_bcm2835_cprman_read(offset, r); --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1601029173913108.78572334793705; Fri, 25 Sep 2020 03:19:33 -0700 (PDT) Received: from localhost ([::1]:47476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kLkpA-00034q-Et for importer@patchew.org; Fri, 25 Sep 2020 06:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42732) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknL-0001Ai-Ek; Fri, 25 Sep 2020 06:17:39 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58234) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknF-0007Rz-37; Fri, 25 Sep 2020 06:17:39 -0400 Received: from sekoia-pc.bar.greensocs.com (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id 6BFA2C60F1F; Fri, 25 Sep 2020 10:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VJd34/7OS7c3o3033uLyqBxQ35yFAlW7/56yUtCbDKg=; b=JCmSYYDLEbwJgFipqAmgDebYuVqPqI6Vjz/hquCUhN20ksa1DFNvvTHHf6U9alL4o7DKUf 9/JPegsE1/hwJYYCsSCmX+KWL2ES10PX5Guc/dma5DPMxIF7522BEvLJ/YwNByP+GgjFv4 tztbV2NppBDE+ywIW2YcVfbAqqxnMIYEoJWXHYU4ybfFDbSMcQCrKae9xfxK9Ehtu4n7rP iQhGDMOT6/kXkubI138IslrAexV7wyA3jrMz3SQGchzztPXyC7GNlis5DYETuS9PVEHTtM aXZcXJm0fzOEtTLzUBZeNCTx8NrD9cTO9sNMK2WEy5LyAi3sXNJkPAqvZxC8cg== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 07/14] hw/misc/bcm2835_cprman: add a PLL channel skeleton implementation Date: Fri, 25 Sep 2020 12:17:24 +0200 Message-Id: <20200925101731.2159827-8-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VJd34/7OS7c3o3033uLyqBxQ35yFAlW7/56yUtCbDKg=; b=LKijZJOnCkHum6eroKJk5/laZPpWnho9kA43J1WLVFbdstpmxE4IkakhS7+h/Kww6NYuUd 3YscgPgKyj1qiBesHCBwc1JBsyF8TK46mzaF6fISAUcuU9ZO2cAnfEXIfIBuKkodJU/Inq OvLasKhhCx3EIw75VMt8Ev68c1S5SMltUE6Y4VB4rJVMVZ6/2CxpdqQHpWiVBFGwTHoODr hAc0umDMHZGSYJ+zDWBANlIPQBVz8tXJakm5F9OzQBi6+EWB44F+i/BLg2FtknjdBj0wXU gw9meKSYXN6OVWj3H43cTq40jHjhKEm2uuxQQq1dnpHwwUfn1KsipvRKY81r+g== ARC-Seal: i=1; s=pharaoh; d=lmichel.fr; t=1601029040; a=rsa-sha256; cv=none; b=SUGHgptDCcJk1/8g1qiRzGdPfqg2luIOqPaikMBVLfvIA9PjM6qxivq+D+0jhtsgQAmrUeGTT0T1lEzODGs0SjjcR+F3Xc3FYeLF8xXjYrcAZkFNstfMijLVgrMdZrJdn4LgoyiUSEQBu2u5B8Im91yK5lUwtbm6culL6gpNrLgvtOxsbaXo4B2FELeDviw2UUJO2/tqr6X6+WMNel0hBji/uDNNInhGnpQ0nVWbGAGf2lNXUMCGzhoKD6nnGQ2yd68yoM9qLvpdxkVyvL+sizBNnul6FnGaqeEKxQ0e+uvBX2oI+be3JtcWFnfFYHn7HhAYBcWaF/afOx9E3jJf2A== ARC-Authentication-Results: i=1; pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" PLLs are composed of multiple channels. Each channel outputs one clock signal. They are modeled as one device taking the PLL generated clock as input, and outputting a new clock. A channel shares the cm register with its parent PLL, and has its own a2w_ctrl register. A write to the cm register will trigger an update of the PLL and all its channels, while a write to an a2w_ctrl channel register will update the required channel only. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/bcm2835_cprman.h | 44 ++++++ include/hw/misc/bcm2835_cprman_internals.h | 146 +++++++++++++++++++ hw/misc/bcm2835_cprman.c | 155 +++++++++++++++++++-- 3 files changed, 337 insertions(+), 8 deletions(-) diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr= man.h index f186ab0104..aaf15fb20c 100644 --- a/include/hw/misc/bcm2835_cprman.h +++ b/include/hw/misc/bcm2835_cprman.h @@ -29,10 +29,35 @@ typedef enum CprmanPLL { CPRMAN_PLLB, =20 CPRMAN_NUM_PLL } CprmanPLL; =20 +typedef enum CprmanPLLChannel { + CPRMAN_PLLA_CHANNEL_DSI0 =3D 0, + CPRMAN_PLLA_CHANNEL_CORE, + CPRMAN_PLLA_CHANNEL_PER, + CPRMAN_PLLA_CHANNEL_CCP2, + + CPRMAN_PLLC_CHANNEL_CORE2, + CPRMAN_PLLC_CHANNEL_CORE1, + CPRMAN_PLLC_CHANNEL_PER, + CPRMAN_PLLC_CHANNEL_CORE0, + + CPRMAN_PLLD_CHANNEL_DSI0, + CPRMAN_PLLD_CHANNEL_CORE, + CPRMAN_PLLD_CHANNEL_PER, + CPRMAN_PLLD_CHANNEL_DSI1, + + CPRMAN_PLLH_CHANNEL_AUX, + CPRMAN_PLLH_CHANNEL_RCAL, + CPRMAN_PLLH_CHANNEL_PIX, + + CPRMAN_PLLB_CHANNEL_ARM, + + CPRMAN_NUM_PLL_CHANNEL, +} CprmanPLLChannel; + typedef struct CprmanPLLState { /*< private >*/ DeviceState parent_obj; =20 /*< public >*/ @@ -46,18 +71,37 @@ typedef struct CprmanPLLState { =20 Clock *xosc_in; Clock *out; } CprmanPLLState; =20 +typedef struct CprmanPLLChannelState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CprmanPLLChannel id; + CprmanPLL parent; + + uint32_t *reg_cm; + uint32_t hold_mask; + uint32_t load_mask; + uint32_t *reg_a2w_ctrl; + int fixed_divider; + + Clock *pll_in; + Clock *out; +} CprmanPLLChannelState; + struct BCM2835CprmanState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; =20 CprmanPLLState plls[CPRMAN_NUM_PLL]; + CprmanPLLChannelState channels[CPRMAN_NUM_PLL_CHANNEL]; =20 uint32_t regs[CPRMAN_NUM_REGS]; uint32_t xosc_freq; =20 Clock *xosc; diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index 22a2500ab0..8a5b9aae67 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -11,13 +11,16 @@ =20 #include "hw/registerfields.h" #include "hw/misc/bcm2835_cprman.h" =20 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll" +#define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel" =20 DECLARE_INSTANCE_CHECKER(CprmanPLLState, CPRMAN_PLL, TYPE_CPRMAN_PLL) +DECLARE_INSTANCE_CHECKER(CprmanPLLChannelState, CPRMAN_PLL_CHANNEL, + TYPE_CPRMAN_PLL_CHANNEL) =20 /* Register map */ =20 /* PLLs */ REG32(CM_PLLA, 0x104) @@ -98,10 +101,35 @@ REG32(A2W_PLLA_FRAC, 0x1200) REG32(A2W_PLLC_FRAC, 0x1220) REG32(A2W_PLLD_FRAC, 0x1240) REG32(A2W_PLLH_FRAC, 0x1260) REG32(A2W_PLLB_FRAC, 0x12e0) =20 +/* PLL channels */ +REG32(A2W_PLLA_DSI0, 0x1300) + FIELD(A2W_PLLx_CHANNELy, DIV, 0, 8) + FIELD(A2W_PLLx_CHANNELy, DISABLE, 8, 1) +REG32(A2W_PLLA_CORE, 0x1400) +REG32(A2W_PLLA_PER, 0x1500) +REG32(A2W_PLLA_CCP2, 0x1600) + +REG32(A2W_PLLC_CORE2, 0x1320) +REG32(A2W_PLLC_CORE1, 0x1420) +REG32(A2W_PLLC_PER, 0x1520) +REG32(A2W_PLLC_CORE0, 0x1620) + +REG32(A2W_PLLD_DSI0, 0x1340) +REG32(A2W_PLLD_CORE, 0x1440) +REG32(A2W_PLLD_PER, 0x1540) +REG32(A2W_PLLD_DSI1, 0x1640) + +REG32(A2W_PLLH_AUX, 0x1360) +REG32(A2W_PLLH_RCAL, 0x1460) +REG32(A2W_PLLH_PIX, 0x1560) +REG32(A2W_PLLH_STS, 0x1660) + +REG32(A2W_PLLB_ARM, 0x13e0) + /* misc registers */ REG32(CM_LOCK, 0x114) FIELD(CM_LOCK, FLOCKH, 12, 1) FIELD(CM_LOCK, FLOCKD, 11, 1) FIELD(CM_LOCK, FLOCKC, 10, 1) @@ -171,6 +199,124 @@ static inline void set_pll_init_info(BCM2835CprmanSta= te *s, pll->reg_a2w_ana =3D &s->regs[PLL_INIT_INFO[id].a2w_ana_offset]; pll->prediv_mask =3D PLL_INIT_INFO[id].prediv_mask; pll->reg_a2w_frac =3D &s->regs[PLL_INIT_INFO[id].a2w_frac_offset]; } =20 + +/* PLL channel init info */ +typedef struct PLLChannelInitInfo { + const char *name; + CprmanPLL parent; + size_t cm_offset; + uint32_t cm_hold_mask; + uint32_t cm_load_mask; + size_t a2w_ctrl_offset; + unsigned int fixed_divider; +} PLLChannelInitInfo; + +#define FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_) \ + .parent =3D CPRMAN_ ## pll_, \ + .cm_offset =3D R_CM_ ## pll_, \ + .cm_load_mask =3D R_CM_ ## pll_ ## _ ## LOAD ## channel_ ## _MASK, \ + .a2w_ctrl_offset =3D R_A2W_ ## pll_ ## _ ## channel_ + +#define FILL_PLL_CHANNEL_INIT_INFO(pll_, channel_) \ + FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \ + .cm_hold_mask =3D R_CM_ ## pll_ ## _ ## HOLD ## channel_ ## _MASK, \ + .fixed_divider =3D 1 + +#define FILL_PLL_CHANNEL_INIT_INFO_nohold(pll_, channel_) \ + FILL_PLL_CHANNEL_INIT_INFO_common(pll_, channel_), \ + .cm_hold_mask =3D 0 + +static PLLChannelInitInfo PLL_CHANNEL_INIT_INFO[] =3D { + [CPRMAN_PLLA_CHANNEL_DSI0] =3D { + .name =3D "plla-dsi0", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, DSI0), + }, + [CPRMAN_PLLA_CHANNEL_CORE] =3D { + .name =3D "plla-core", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, CORE), + }, + [CPRMAN_PLLA_CHANNEL_PER] =3D { + .name =3D "plla-per", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, PER), + }, + [CPRMAN_PLLA_CHANNEL_CCP2] =3D { + .name =3D "plla-ccp2", + FILL_PLL_CHANNEL_INIT_INFO(PLLA, CCP2), + }, + + [CPRMAN_PLLC_CHANNEL_CORE2] =3D { + .name =3D "pllc-core2", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE2), + }, + [CPRMAN_PLLC_CHANNEL_CORE1] =3D { + .name =3D "pllc-core1", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE1), + }, + [CPRMAN_PLLC_CHANNEL_PER] =3D { + .name =3D "pllc-per", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, PER), + }, + [CPRMAN_PLLC_CHANNEL_CORE0] =3D { + .name =3D "pllc-core0", + FILL_PLL_CHANNEL_INIT_INFO(PLLC, CORE0), + }, + + [CPRMAN_PLLD_CHANNEL_DSI0] =3D { + .name =3D "plld-dsi0", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI0), + }, + [CPRMAN_PLLD_CHANNEL_CORE] =3D { + .name =3D "plld-core", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, CORE), + }, + [CPRMAN_PLLD_CHANNEL_PER] =3D { + .name =3D "plld-per", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, PER), + }, + [CPRMAN_PLLD_CHANNEL_DSI1] =3D { + .name =3D "plld-dsi1", + FILL_PLL_CHANNEL_INIT_INFO(PLLD, DSI1), + }, + + [CPRMAN_PLLH_CHANNEL_AUX] =3D { + .name =3D "pllh-aux", + .fixed_divider =3D 1, + FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, AUX), + }, + [CPRMAN_PLLH_CHANNEL_RCAL] =3D { + .name =3D "pllh-rcal", + .fixed_divider =3D 10, + FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, RCAL), + }, + [CPRMAN_PLLH_CHANNEL_PIX] =3D { + .name =3D "pllh-pix", + .fixed_divider =3D 10, + FILL_PLL_CHANNEL_INIT_INFO_nohold(PLLH, PIX), + }, + + [CPRMAN_PLLB_CHANNEL_ARM] =3D { + .name =3D "pllb-arm", + FILL_PLL_CHANNEL_INIT_INFO(PLLB, ARM), + }, +}; + +#undef FILL_PLL_CHANNEL_INIT_INFO_nohold +#undef FILL_PLL_CHANNEL_INIT_INFO +#undef FILL_PLL_CHANNEL_INIT_INFO_common + +static inline void set_pll_channel_init_info(BCM2835CprmanState *s, + CprmanPLLChannelState *channe= l, + CprmanPLLChannel id) +{ + channel->id =3D id; + channel->parent =3D PLL_CHANNEL_INIT_INFO[id].parent; + channel->reg_cm =3D &s->regs[PLL_CHANNEL_INIT_INFO[id].cm_offset]; + channel->hold_mask =3D PLL_CHANNEL_INIT_INFO[id].cm_hold_mask; + channel->load_mask =3D PLL_CHANNEL_INIT_INFO[id].cm_load_mask; + channel->reg_a2w_ctrl =3D &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_= offset]; + channel->fixed_divider =3D PLL_CHANNEL_INIT_INFO[id].fixed_divider; +} + #endif diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index ba82522eb1..2c70a3f317 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -130,10 +130,73 @@ static const TypeInfo cprman_pll_info =3D { .class_init =3D pll_class_init, .instance_init =3D pll_init, }; =20 =20 +/* PLL channel */ + +static void pll_channel_update(CprmanPLLChannelState *channel) +{ + clock_update(channel->out, 0); +} + +/* Update a PLL and all its channels */ +static void pll_update_all_channels(BCM2835CprmanState *s, + CprmanPLLState *pll) +{ + size_t i; + + pll_update(pll); + + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + CprmanPLLChannelState *channel =3D &s->channels[i]; + if (channel->parent =3D=3D pll->id) { + pll_channel_update(channel); + } + } +} + +static void pll_channel_pll_in_update(void *opaque) +{ + pll_channel_update(CPRMAN_PLL_CHANNEL(opaque)); +} + +static void pll_channel_init(Object *obj) +{ + CprmanPLLChannelState *s =3D CPRMAN_PLL_CHANNEL(obj); + + s->pll_in =3D qdev_init_clock_in(DEVICE(s), "pll-in", + pll_channel_pll_in_update, s); + s->out =3D qdev_init_clock_out(DEVICE(s), "out"); +} + +static const VMStateDescription pll_channel_vmstate =3D { + .name =3D TYPE_CPRMAN_PLL_CHANNEL, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(pll_in, CprmanPLLChannelState), + VMSTATE_END_OF_LIST() + } +}; + +static void pll_channel_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &pll_channel_vmstate; +} + +static const TypeInfo cprman_pll_channel_info =3D { + .name =3D TYPE_CPRMAN_PLL_CHANNEL, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CprmanPLLChannelState), + .class_init =3D pll_channel_class_init, + .instance_init =3D pll_channel_init, +}; + + /* CPRMAN "top level" model */ =20 static uint32_t get_cm_lock(const BCM2835CprmanState *s) { static const int CM_LOCK_MAPPING[] =3D { @@ -172,12 +235,36 @@ static uint64_t cprman_read(void *opaque, hwaddr offs= et, =20 trace_bcm2835_cprman_read(offset, r); return r; } =20 -#define CASE_PLL_REGS(pll_) \ - case R_CM_ ## pll_: \ +static inline void update_pll_and_channels_from_cm(BCM2835CprmanState *s, + size_t idx) +{ + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { + if (PLL_INIT_INFO[i].cm_offset =3D=3D idx) { + pll_update_all_channels(s, &s->plls[i]); + return; + } + } +} + +static inline void update_channel_from_a2w(BCM2835CprmanState *s, size_t i= dx) +{ + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + if (PLL_CHANNEL_INIT_INFO[i].a2w_ctrl_offset =3D=3D idx) { + pll_channel_update(&s->channels[i]); + return; + } + } +} + +#define CASE_PLL_A2W_REGS(pll_) \ case R_A2W_ ## pll_ ## _CTRL: \ case R_A2W_ ## pll_ ## _ANA0: \ case R_A2W_ ## pll_ ## _ANA1: \ case R_A2W_ ## pll_ ## _ANA2: \ case R_A2W_ ## pll_ ## _ANA3: \ @@ -198,33 +285,61 @@ static void cprman_write(void *opaque, hwaddr offset, =20 trace_bcm2835_cprman_write(offset, value); s->regs[idx] =3D value; =20 switch (idx) { - CASE_PLL_REGS(PLLA) : + case R_CM_PLLA ... R_CM_PLLH: + case R_CM_PLLB: + /* + * A given CM_PLLx register is shared by both the PLL and the chan= nels + * of this PLL. + */ + update_pll_and_channels_from_cm(s, idx); + break; + + CASE_PLL_A2W_REGS(PLLA) : pll_update(&s->plls[CPRMAN_PLLA]); break; =20 - CASE_PLL_REGS(PLLC) : + CASE_PLL_A2W_REGS(PLLC) : pll_update(&s->plls[CPRMAN_PLLC]); break; =20 - CASE_PLL_REGS(PLLD) : + CASE_PLL_A2W_REGS(PLLD) : pll_update(&s->plls[CPRMAN_PLLD]); break; =20 - CASE_PLL_REGS(PLLH) : + CASE_PLL_A2W_REGS(PLLH) : pll_update(&s->plls[CPRMAN_PLLH]); break; =20 - CASE_PLL_REGS(PLLB) : + CASE_PLL_A2W_REGS(PLLB) : pll_update(&s->plls[CPRMAN_PLLB]); break; + + case R_A2W_PLLA_DSI0: + case R_A2W_PLLA_CORE: + case R_A2W_PLLA_PER: + case R_A2W_PLLA_CCP2: + case R_A2W_PLLC_CORE2: + case R_A2W_PLLC_CORE1: + case R_A2W_PLLC_PER: + case R_A2W_PLLC_CORE0: + case R_A2W_PLLD_DSI0: + case R_A2W_PLLD_CORE: + case R_A2W_PLLD_PER: + case R_A2W_PLLD_DSI1: + case R_A2W_PLLH_AUX: + case R_A2W_PLLH_RCAL: + case R_A2W_PLLH_PIX: + case R_A2W_PLLB_ARM: + update_channel_from_a2w(s, idx); + break; } } =20 -#undef CASE_PLL_REGS +#undef CASE_PLL_A2W_REGS =20 static const MemoryRegionOps cprman_ops =3D { .read =3D cprman_read, .write =3D cprman_write, .endianness =3D DEVICE_LITTLE_ENDIAN, @@ -244,10 +359,14 @@ static void cprman_reset(DeviceState *dev) =20 for (i =3D 0; i < CPRMAN_NUM_PLL; i++) { device_cold_reset(DEVICE(&s->plls[i])); } =20 + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + device_cold_reset(DEVICE(&s->channels[i])); + } + clock_update_hz(s->xosc, s->xosc_freq); } =20 static Clock *init_internal_clock(BCM2835CprmanState *s, const char *name) @@ -274,10 +393,17 @@ static void cprman_init(Object *obj) object_initialize_child(obj, PLL_INIT_INFO[i].name, &s->plls[i], TYPE_CPRMAN_PLL); set_pll_init_info(s, &s->plls[i], i); } =20 + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + object_initialize_child(obj, PLL_CHANNEL_INIT_INFO[i].name, + &s->channels[i], + TYPE_CPRMAN_PLL_CHANNEL); + set_pll_channel_init_info(s, &s->channels[i], i); + } + s->xosc =3D init_internal_clock(s, "xosc"); =20 memory_region_init_io(&s->iomem, obj, &cprman_ops, s, "bcm2835-cprman", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); @@ -295,10 +421,22 @@ static void cprman_realize(DeviceState *dev, Error **= errp) =20 if (!qdev_realize(DEVICE(pll), NULL, errp)) { return; } } + + for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { + CprmanPLLChannelState *channel =3D &s->channels[i]; + CprmanPLL parent =3D PLL_CHANNEL_INIT_INFO[i].parent; + Clock *parent_clk =3D s->plls[parent].out; + + clock_set_source(channel->pll_in, parent_clk); + + if (!qdev_realize(DEVICE(channel), NULL, errp)) { + return; + } + } } =20 static const VMStateDescription cprman_vmstate =3D { .name =3D TYPE_BCM2835_CPRMAN, .version_id =3D 1, @@ -334,8 +472,9 @@ static const TypeInfo cprman_info =3D { =20 static void cprman_register_types(void) { type_register_static(&cprman_info); type_register_static(&cprman_pll_info); + type_register_static(&cprman_pll_channel_info); } =20 type_init(cprman_register_types); --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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charset="utf-8" A PLL channel is able to further divide the generated PLL frequency. The divider is given in the ctrl_a2w register. Some channels have a additional fixed divider which is always applied to the signal. Signed-off-by: Luc Michel Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/bcm2835_cprman.c | 33 ++++++++++++++++++++++++++++++++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 2c70a3f317..e644aeb2b5 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -132,13 +132,44 @@ static const TypeInfo cprman_pll_info =3D { }; =20 =20 /* PLL channel */ =20 +static bool pll_channel_is_enabled(CprmanPLLChannelState *channel) +{ + /* + * XXX I'm not sure of the purpose of the LOAD field. The Linux driver= does + * not set it when enabling the channel, but does clear it when disabl= ing + * it. + */ + return !FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DISABLE) + && !(*channel->reg_cm & channel->hold_mask); +} + static void pll_channel_update(CprmanPLLChannelState *channel) { - clock_update(channel->out, 0); + uint64_t freq, div; + + if (!pll_channel_is_enabled(channel)) { + clock_update(channel->out, 0); + return; + } + + div =3D FIELD_EX32(*channel->reg_a2w_ctrl, A2W_PLLx_CHANNELy, DIV); + + if (!div) { + /* + * It seems that when the divider value is 0, it is considered as + * being maximum by the hardware (see the Linux driver). + */ + div =3D R_A2W_PLLx_CHANNELy_DIV_MASK; + } + + /* Some channels have an additional fixed divider */ + freq =3D clock_get_hz(channel->pll_in) / (div * channel->fixed_divider= ); + + clock_update_hz(channel->out, freq); } =20 /* Update a PLL and all its channels */ static void pll_update_all_channels(BCM2835CprmanState *s, CprmanPLLState *pll) --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1601029786642102.82924526552017; Fri, 25 Sep 2020 03:29:46 -0700 (PDT) Received: from localhost ([::1]:47526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kLkz3-0006yf-3F for importer@patchew.org; Fri, 25 Sep 2020 06:29:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknn-0001cp-Rb; Fri, 25 Sep 2020 06:18:07 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58238) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknd-0007SF-9O; Fri, 25 Sep 2020 06:18:07 -0400 Received: from sekoia-pc.bar.greensocs.com (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id 97D56C60F21; Fri, 25 Sep 2020 10:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=v/uiZF1SCdR1bRANIJzuR1+OmsRilHDQs3qMfJu0mlc=; b=Ny5gMLcIT5LVGwu96dSmeIQMW6zMOS44WIGOXbpT98YGM9Dk+ub9nLyQhN7DkCHNy5ovbi 8NyOJxZVzcN4DecaVT2SSyzcM0hYnaUVrdqYN3qPnNodWv8PtQe6zRMRQCI4Eu8LgKnqMq brga4yk4ha3T7IV+8DjqUT53CphM2EEPwNadz9j09dJ5x855d5BqG/fHWbzIBtUuzdZAJl LMZGdqB7tK/BIoTvUO8lObrvr7/yf9Wf9fSFlPIAFB7BHRzKtRVbHofTmUHVyhvg74bef8 9DtjHaRhKfKjxCgX1cc8AIIkmq0DorC3t+7OZ1ktPRuGjagq046DcTHpEhle5w== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 09/14] hw/misc/bcm2835_cprman: add a clock mux skeleton implementation Date: Fri, 25 Sep 2020 12:17:26 +0200 Message-Id: <20200925101731.2159827-10-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; 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pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The clock multiplexers are the last clock stage in the cprman. Each mux outputs one clock signal that goes out of the cprman to the SoC peripherals. Each mux has at most 10 sources. The sources 0 to 3 are common to all muxes. They are: 0. ground (no clock signal) 1. the main oscillator (xosc) 2. "test debug 0" clock 3. "test debug 1" clock Test debug 0 and 1 are actual clock muxes that can be used as sources to other muxes (for debug purpose). Sources 4 to 9 are mux specific and can be unpopulated (grounded). Those sources are fed by the PLL channels outputs. One corner case exists for DSI0E and DSI0P muxes. They have their source number 4 connected to an intermediate multiplexer that can select between PLLA-DSI0 and PLLD-DSI0 channel. This multiplexer is called DSI0HSCK and is not a clock mux as such. It is really a simple mux from the hardware point of view (see https://elinux.org/The_Undocumented_Pi). This mux is not implemented in this commit. Note that there is some muxes for which sources are unknown (because of a lack of documentation). For those cases all the sources are connected to ground in this implementation. Each clock mux output is exported by the cprman at the qdev level, adding the suffix '-out' to the mux name to form the output clock name. (E.g. the 'uart' mux sees its output exported as 'uart-out' at the cprman level.) Signed-off-by: Luc Michel Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/bcm2835_cprman.h | 84 ++++ include/hw/misc/bcm2835_cprman_internals.h | 421 +++++++++++++++++++++ hw/misc/bcm2835_cprman.c | 151 ++++++++ 3 files changed, 656 insertions(+) diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr= man.h index aaf15fb20c..c2a89e8e90 100644 --- a/include/hw/misc/bcm2835_cprman.h +++ b/include/hw/misc/bcm2835_cprman.h @@ -52,12 +52,73 @@ typedef enum CprmanPLLChannel { CPRMAN_PLLH_CHANNEL_PIX, =20 CPRMAN_PLLB_CHANNEL_ARM, =20 CPRMAN_NUM_PLL_CHANNEL, + + /* Special values used when connecting clock sources to clocks */ + CPRMAN_CLOCK_SRC_NORMAL =3D -1, + CPRMAN_CLOCK_SRC_FORCE_GROUND =3D -2, + CPRMAN_CLOCK_SRC_DSI0HSCK =3D -3, } CprmanPLLChannel; =20 +typedef enum CprmanClockMux { + CPRMAN_CLOCK_GNRIC, + CPRMAN_CLOCK_VPU, + CPRMAN_CLOCK_SYS, + CPRMAN_CLOCK_PERIA, + CPRMAN_CLOCK_PERII, + CPRMAN_CLOCK_H264, + CPRMAN_CLOCK_ISP, + CPRMAN_CLOCK_V3D, + CPRMAN_CLOCK_CAM0, + CPRMAN_CLOCK_CAM1, + CPRMAN_CLOCK_CCP2, + CPRMAN_CLOCK_DSI0E, + CPRMAN_CLOCK_DSI0P, + CPRMAN_CLOCK_DPI, + CPRMAN_CLOCK_GP0, + CPRMAN_CLOCK_GP1, + CPRMAN_CLOCK_GP2, + CPRMAN_CLOCK_HSM, + CPRMAN_CLOCK_OTP, + CPRMAN_CLOCK_PCM, + CPRMAN_CLOCK_PWM, + CPRMAN_CLOCK_SLIM, + CPRMAN_CLOCK_SMI, + CPRMAN_CLOCK_TEC, + CPRMAN_CLOCK_TD0, + CPRMAN_CLOCK_TD1, + CPRMAN_CLOCK_TSENS, + CPRMAN_CLOCK_TIMER, + CPRMAN_CLOCK_UART, + CPRMAN_CLOCK_VEC, + CPRMAN_CLOCK_PULSE, + CPRMAN_CLOCK_SDC, + CPRMAN_CLOCK_ARM, + CPRMAN_CLOCK_AVEO, + CPRMAN_CLOCK_EMMC, + CPRMAN_CLOCK_EMMC2, + + CPRMAN_NUM_CLOCK_MUX +} CprmanClockMux; + +typedef enum CprmanClockMuxSource { + CPRMAN_CLOCK_SRC_GND =3D 0, + CPRMAN_CLOCK_SRC_XOSC, + CPRMAN_CLOCK_SRC_TD0, + CPRMAN_CLOCK_SRC_TD1, + CPRMAN_CLOCK_SRC_PLLA, + CPRMAN_CLOCK_SRC_PLLC, + CPRMAN_CLOCK_SRC_PLLD, + CPRMAN_CLOCK_SRC_PLLH, + CPRMAN_CLOCK_SRC_PLLC_CORE1, + CPRMAN_CLOCK_SRC_PLLC_CORE2, + + CPRMAN_NUM_CLOCK_MUX_SRC +} CprmanClockMuxSource; + typedef struct CprmanPLLState { /*< private >*/ DeviceState parent_obj; =20 /*< public >*/ @@ -89,22 +150,45 @@ typedef struct CprmanPLLChannelState { =20 Clock *pll_in; Clock *out; } CprmanPLLChannelState; =20 +typedef struct CprmanClockMuxState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CprmanClockMux id; + + uint32_t *reg_cm; + int int_bits; + int frac_bits; + + Clock *srcs[CPRMAN_NUM_CLOCK_MUX_SRC]; + Clock *out; + + /* + * Used by clock srcs update callback to retrieve both the clock and t= he + * source number. + */ + struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC]; +} CprmanClockMuxState; + struct BCM2835CprmanState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; =20 CprmanPLLState plls[CPRMAN_NUM_PLL]; CprmanPLLChannelState channels[CPRMAN_NUM_PLL_CHANNEL]; + CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX]; =20 uint32_t regs[CPRMAN_NUM_REGS]; uint32_t xosc_freq; =20 Clock *xosc; + Clock *gnd; }; =20 #endif diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index 8a5b9aae67..a2b5a1aa50 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -12,15 +12,18 @@ #include "hw/registerfields.h" #include "hw/misc/bcm2835_cprman.h" =20 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll" #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel" +#define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux" =20 DECLARE_INSTANCE_CHECKER(CprmanPLLState, CPRMAN_PLL, TYPE_CPRMAN_PLL) DECLARE_INSTANCE_CHECKER(CprmanPLLChannelState, CPRMAN_PLL_CHANNEL, TYPE_CPRMAN_PLL_CHANNEL) +DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX, + TYPE_CPRMAN_CLOCK_MUX) =20 /* Register map */ =20 /* PLLs */ REG32(CM_PLLA, 0x104) @@ -126,10 +129,94 @@ REG32(A2W_PLLH_RCAL, 0x1460) REG32(A2W_PLLH_PIX, 0x1560) REG32(A2W_PLLH_STS, 0x1660) =20 REG32(A2W_PLLB_ARM, 0x13e0) =20 +/* Clock muxes */ +REG32(CM_GNRICCTL, 0x000) + FIELD(CM_CLOCKx_CTL, SRC, 0, 4) + FIELD(CM_CLOCKx_CTL, ENABLE, 4, 1) + FIELD(CM_CLOCKx_CTL, KILL, 5, 1) + FIELD(CM_CLOCKx_CTL, GATE, 6, 1) + FIELD(CM_CLOCKx_CTL, BUSY, 7, 1) + FIELD(CM_CLOCKx_CTL, BUSYD, 8, 1) + FIELD(CM_CLOCKx_CTL, MASH, 9, 2) + FIELD(CM_CLOCKx_CTL, FLIP, 11, 1) +REG32(CM_GNRICDIV, 0x004) + FIELD(CM_CLOCKx_DIV, FRAC, 0, 12) +REG32(CM_VPUCTL, 0x008) +REG32(CM_VPUDIV, 0x00c) +REG32(CM_SYSCTL, 0x010) +REG32(CM_SYSDIV, 0x014) +REG32(CM_PERIACTL, 0x018) +REG32(CM_PERIADIV, 0x01c) +REG32(CM_PERIICTL, 0x020) +REG32(CM_PERIIDIV, 0x024) +REG32(CM_H264CTL, 0x028) +REG32(CM_H264DIV, 0x02c) +REG32(CM_ISPCTL, 0x030) +REG32(CM_ISPDIV, 0x034) +REG32(CM_V3DCTL, 0x038) +REG32(CM_V3DDIV, 0x03c) +REG32(CM_CAM0CTL, 0x040) +REG32(CM_CAM0DIV, 0x044) +REG32(CM_CAM1CTL, 0x048) +REG32(CM_CAM1DIV, 0x04c) +REG32(CM_CCP2CTL, 0x050) +REG32(CM_CCP2DIV, 0x054) +REG32(CM_DSI0ECTL, 0x058) +REG32(CM_DSI0EDIV, 0x05c) +REG32(CM_DSI0PCTL, 0x060) +REG32(CM_DSI0PDIV, 0x064) +REG32(CM_DPICTL, 0x068) +REG32(CM_DPIDIV, 0x06c) +REG32(CM_GP0CTL, 0x070) +REG32(CM_GP0DIV, 0x074) +REG32(CM_GP1CTL, 0x078) +REG32(CM_GP1DIV, 0x07c) +REG32(CM_GP2CTL, 0x080) +REG32(CM_GP2DIV, 0x084) +REG32(CM_HSMCTL, 0x088) +REG32(CM_HSMDIV, 0x08c) +REG32(CM_OTPCTL, 0x090) +REG32(CM_OTPDIV, 0x094) +REG32(CM_PCMCTL, 0x098) +REG32(CM_PCMDIV, 0x09c) +REG32(CM_PWMCTL, 0x0a0) +REG32(CM_PWMDIV, 0x0a4) +REG32(CM_SLIMCTL, 0x0a8) +REG32(CM_SLIMDIV, 0x0ac) +REG32(CM_SMICTL, 0x0b0) +REG32(CM_SMIDIV, 0x0b4) +REG32(CM_TCNTCTL, 0x0c0) +REG32(CM_TCNTCNT, 0x0c4) +REG32(CM_TECCTL, 0x0c8) +REG32(CM_TECDIV, 0x0cc) +REG32(CM_TD0CTL, 0x0d0) +REG32(CM_TD0DIV, 0x0d4) +REG32(CM_TD1CTL, 0x0d8) +REG32(CM_TD1DIV, 0x0dc) +REG32(CM_TSENSCTL, 0x0e0) +REG32(CM_TSENSDIV, 0x0e4) +REG32(CM_TIMERCTL, 0x0e8) +REG32(CM_TIMERDIV, 0x0ec) +REG32(CM_UARTCTL, 0x0f0) +REG32(CM_UARTDIV, 0x0f4) +REG32(CM_VECCTL, 0x0f8) +REG32(CM_VECDIV, 0x0fc) +REG32(CM_PULSECTL, 0x190) +REG32(CM_PULSEDIV, 0x194) +REG32(CM_SDCCTL, 0x1a8) +REG32(CM_SDCDIV, 0x1ac) +REG32(CM_ARMCTL, 0x1b0) +REG32(CM_AVEOCTL, 0x1b8) +REG32(CM_AVEODIV, 0x1bc) +REG32(CM_EMMCCTL, 0x1c0) +REG32(CM_EMMCDIV, 0x1c4) +REG32(CM_EMMC2CTL, 0x1d0) +REG32(CM_EMMC2DIV, 0x1d4) + /* misc registers */ REG32(CM_LOCK, 0x114) FIELD(CM_LOCK, FLOCKH, 12, 1) FIELD(CM_LOCK, FLOCKD, 11, 1) FIELD(CM_LOCK, FLOCKC, 10, 1) @@ -317,6 +404,340 @@ static inline void set_pll_channel_init_info(BCM2835C= prmanState *s, channel->load_mask =3D PLL_CHANNEL_INIT_INFO[id].cm_load_mask; channel->reg_a2w_ctrl =3D &s->regs[PLL_CHANNEL_INIT_INFO[id].a2w_ctrl_= offset]; channel->fixed_divider =3D PLL_CHANNEL_INIT_INFO[id].fixed_divider; } =20 +/* Clock mux init info */ +typedef struct ClockMuxInitInfo { + const char *name; + size_t cm_offset; + int int_bits; + int frac_bits; + + CprmanPLLChannel src_mapping[CPRMAN_NUM_CLOCK_MUX_SRC]; +} ClockMuxInitInfo; + +/* + * Each clock mux can have up to 10 sources. Sources 0 to 3 are always the + * same (ground, xosc, td0, td1). Sources 4 to 9 are mux specific, and are= not + * always populated. The following macros catch all those cases. + */ + +/* Unknown mapping. Connect everything to ground */ +#define SRC_MAPPING_INFO_unknown \ + .src_mapping =3D { \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* gnd */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* xosc */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 0 */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* test debug 1 */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll a */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll d */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll h */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core1 */ \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, /* pll c, core2 */ \ + } + +/* Only the oscillator and the two test debug clocks */ +#define SRC_MAPPING_INFO_xosc \ + .src_mapping =3D { \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + } + +/* All the PLL "core" channels */ +#define SRC_MAPPING_INFO_core \ + .src_mapping =3D { \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_PLLA_CHANNEL_CORE, \ + CPRMAN_PLLC_CHANNEL_CORE0, \ + CPRMAN_PLLD_CHANNEL_CORE, \ + CPRMAN_PLLH_CHANNEL_AUX, \ + CPRMAN_PLLC_CHANNEL_CORE1, \ + CPRMAN_PLLC_CHANNEL_CORE2, \ + } + +/* All the PLL "per" channels */ +#define SRC_MAPPING_INFO_periph \ + .src_mapping =3D { \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_PLLA_CHANNEL_PER, \ + CPRMAN_PLLC_CHANNEL_PER, \ + CPRMAN_PLLD_CHANNEL_PER, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + } + +/* + * The DSI0 channels. This one got an intermediate mux between the PLL cha= nnels + * and the clock input. + */ +#define SRC_MAPPING_INFO_dsi0 \ + .src_mapping =3D { \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_DSI0HSCK, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + } + +/* The DSI1 channel */ +#define SRC_MAPPING_INFO_dsi1 \ + .src_mapping =3D { \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_CLOCK_SRC_NORMAL, \ + CPRMAN_PLLD_CHANNEL_DSI1, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + CPRMAN_CLOCK_SRC_FORCE_GROUND, \ + } + +#define FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_) \ + SRC_MAPPING_INFO_ ## kind_ + +#define FILL_CLOCK_MUX_INIT_INFO(clock_, kind_) \ + .cm_offset =3D R_CM_ ## clock_ ## CTL, \ + FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO(kind_) + +static ClockMuxInitInfo CLOCK_MUX_INIT_INFO[] =3D { + [CPRMAN_CLOCK_GNRIC] =3D { + .name =3D "gnric", + FILL_CLOCK_MUX_INIT_INFO(GNRIC, unknown), + }, + [CPRMAN_CLOCK_VPU] =3D { + .name =3D "vpu", + .int_bits =3D 12, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(VPU, core), + }, + [CPRMAN_CLOCK_SYS] =3D { + .name =3D "sys", + FILL_CLOCK_MUX_INIT_INFO(SYS, unknown), + }, + [CPRMAN_CLOCK_PERIA] =3D { + .name =3D "peria", + FILL_CLOCK_MUX_INIT_INFO(PERIA, unknown), + }, + [CPRMAN_CLOCK_PERII] =3D { + .name =3D "perii", + FILL_CLOCK_MUX_INIT_INFO(PERII, unknown), + }, + [CPRMAN_CLOCK_H264] =3D { + .name =3D "h264", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(H264, core), + }, + [CPRMAN_CLOCK_ISP] =3D { + .name =3D "isp", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(ISP, core), + }, + [CPRMAN_CLOCK_V3D] =3D { + .name =3D "v3d", + FILL_CLOCK_MUX_INIT_INFO(V3D, core), + }, + [CPRMAN_CLOCK_CAM0] =3D { + .name =3D "cam0", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(CAM0, periph), + }, + [CPRMAN_CLOCK_CAM1] =3D { + .name =3D "cam1", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(CAM1, periph), + }, + [CPRMAN_CLOCK_CCP2] =3D { + .name =3D "ccp2", + FILL_CLOCK_MUX_INIT_INFO(CCP2, unknown), + }, + [CPRMAN_CLOCK_DSI0E] =3D { + .name =3D "dsi0e", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(DSI0E, dsi0), + }, + [CPRMAN_CLOCK_DSI0P] =3D { + .name =3D "dsi0p", + .int_bits =3D 0, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(DSI0P, dsi0), + }, + [CPRMAN_CLOCK_DPI] =3D { + .name =3D "dpi", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(DPI, periph), + }, + [CPRMAN_CLOCK_GP0] =3D { + .name =3D "gp0", + .int_bits =3D 12, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(GP0, periph), + }, + [CPRMAN_CLOCK_GP1] =3D { + .name =3D "gp1", + .int_bits =3D 12, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(GP1, periph), + }, + [CPRMAN_CLOCK_GP2] =3D { + .name =3D "gp2", + .int_bits =3D 12, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(GP2, periph), + }, + [CPRMAN_CLOCK_HSM] =3D { + .name =3D "hsm", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(HSM, periph), + }, + [CPRMAN_CLOCK_OTP] =3D { + .name =3D "otp", + .int_bits =3D 4, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(OTP, xosc), + }, + [CPRMAN_CLOCK_PCM] =3D { + .name =3D "pcm", + .int_bits =3D 12, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(PCM, periph), + }, + [CPRMAN_CLOCK_PWM] =3D { + .name =3D "pwm", + .int_bits =3D 12, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(PWM, periph), + }, + [CPRMAN_CLOCK_SLIM] =3D { + .name =3D "slim", + .int_bits =3D 12, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(SLIM, periph), + }, + [CPRMAN_CLOCK_SMI] =3D { + .name =3D "smi", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(SMI, periph), + }, + [CPRMAN_CLOCK_TEC] =3D { + .name =3D "tec", + .int_bits =3D 6, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(TEC, xosc), + }, + [CPRMAN_CLOCK_TD0] =3D { + .name =3D "td0", + FILL_CLOCK_MUX_INIT_INFO(TD0, unknown), + }, + [CPRMAN_CLOCK_TD1] =3D { + .name =3D "td1", + FILL_CLOCK_MUX_INIT_INFO(TD1, unknown), + }, + [CPRMAN_CLOCK_TSENS] =3D { + .name =3D "tsens", + .int_bits =3D 5, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(TSENS, xosc), + }, + [CPRMAN_CLOCK_TIMER] =3D { + .name =3D "timer", + .int_bits =3D 6, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(TIMER, xosc), + }, + [CPRMAN_CLOCK_UART] =3D { + .name =3D "uart", + .int_bits =3D 10, + .frac_bits =3D 12, + FILL_CLOCK_MUX_INIT_INFO(UART, periph), + }, + [CPRMAN_CLOCK_VEC] =3D { + .name =3D "vec", + .int_bits =3D 4, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(VEC, periph), + }, + [CPRMAN_CLOCK_PULSE] =3D { + .name =3D "pulse", + FILL_CLOCK_MUX_INIT_INFO(PULSE, xosc), + }, + [CPRMAN_CLOCK_SDC] =3D { + .name =3D "sdram", + .int_bits =3D 6, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(SDC, core), + }, + [CPRMAN_CLOCK_ARM] =3D { + .name =3D "arm", + FILL_CLOCK_MUX_INIT_INFO(ARM, unknown), + }, + [CPRMAN_CLOCK_AVEO] =3D { + .name =3D "aveo", + .int_bits =3D 4, + .frac_bits =3D 0, + FILL_CLOCK_MUX_INIT_INFO(AVEO, periph), + }, + [CPRMAN_CLOCK_EMMC] =3D { + .name =3D "emmc", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(EMMC, periph), + }, + [CPRMAN_CLOCK_EMMC2] =3D { + .name =3D "emmc2", + .int_bits =3D 4, + .frac_bits =3D 8, + FILL_CLOCK_MUX_INIT_INFO(EMMC2, unknown), + }, +}; + +#undef FILL_CLOCK_MUX_INIT_INFO +#undef FILL_CLOCK_MUX_SRC_MAPPING_INIT_INFO +#undef SRC_MAPPING_INFO_dsi1 +#undef SRC_MAPPING_INFO_dsi0 +#undef SRC_MAPPING_INFO_periph +#undef SRC_MAPPING_INFO_core +#undef SRC_MAPPING_INFO_xosc +#undef SRC_MAPPING_INFO_unknown + +static inline void set_clock_mux_init_info(BCM2835CprmanState *s, + CprmanClockMuxState *mux, + CprmanClockMux id) +{ + mux->id =3D id; + mux->reg_cm =3D &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset]; + mux->int_bits =3D CLOCK_MUX_INIT_INFO[id].int_bits; + mux->frac_bits =3D CLOCK_MUX_INIT_INFO[id].frac_bits; +} + #endif diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index e644aeb2b5..8df2db0fd9 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -36,10 +36,13 @@ * | [mux] * \-->[PLL]--->[PLL channel] [mux] * * The page at https://elinux.org/The_Undocumented_Pi gives the actual clo= ck * tree configuration. + * + * The CPRMAN exposes clock outputs with the name of the clock mux suffixed + * with "-out" (e.g. "uart-out", "h264-out", ...). */ =20 #include "qemu/osdep.h" #include "qemu/log.h" #include "migration/vmstate.h" @@ -224,10 +227,69 @@ static const TypeInfo cprman_pll_channel_info =3D { .class_init =3D pll_channel_class_init, .instance_init =3D pll_channel_init, }; =20 =20 +/* clock mux */ + +static void clock_mux_update(CprmanClockMuxState *mux) +{ + clock_update(mux->out, 0); +} + +static void clock_mux_src_update(void *opaque) +{ + CprmanClockMuxState **backref =3D opaque; + CprmanClockMuxState *s =3D *backref; + + clock_mux_update(s); +} + +static void clock_mux_init(Object *obj) +{ + CprmanClockMuxState *s =3D CPRMAN_CLOCK_MUX(obj); + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) { + char *name =3D g_strdup_printf("srcs[%zu]", i); + s->backref[i] =3D s; + s->srcs[i] =3D qdev_init_clock_in(DEVICE(s), name, + clock_mux_src_update, + &s->backref[i]); + g_free(name); + } + + s->out =3D qdev_init_clock_out(DEVICE(s), "out"); +} + +static const VMStateDescription clock_mux_vmstate =3D { + .name =3D TYPE_CPRMAN_CLOCK_MUX, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_ARRAY_CLOCK(srcs, CprmanClockMuxState, + CPRMAN_NUM_CLOCK_MUX_SRC), + VMSTATE_END_OF_LIST() + } +}; + +static void clock_mux_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &clock_mux_vmstate; +} + +static const TypeInfo cprman_clock_mux_info =3D { + .name =3D TYPE_CPRMAN_CLOCK_MUX, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CprmanClockMuxState), + .class_init =3D clock_mux_class_init, + .instance_init =3D clock_mux_init, +}; + + /* CPRMAN "top level" model */ =20 static uint32_t get_cm_lock(const BCM2835CprmanState *s) { static const int CM_LOCK_MAPPING[] =3D { @@ -291,10 +353,23 @@ static inline void update_channel_from_a2w(BCM2835Cpr= manState *s, size_t idx) return; } } } =20 +static inline void update_mux_from_cm(BCM2835CprmanState *s, size_t idx) +{ + size_t i; + + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { + if ((CLOCK_MUX_INIT_INFO[i].cm_offset =3D=3D idx) + || (CLOCK_MUX_INIT_INFO[i].cm_offset =3D=3D idx + 4)) { + clock_mux_update(&s->clock_muxes[i]); + return; + } + } +} + #define CASE_PLL_A2W_REGS(pll_) \ case R_A2W_ ## pll_ ## _CTRL: \ case R_A2W_ ## pll_ ## _ANA0: \ case R_A2W_ ## pll_ ## _ANA1: \ case R_A2W_ ## pll_ ## _ANA2: \ @@ -363,10 +438,19 @@ static void cprman_write(void *opaque, hwaddr offset, case R_A2W_PLLH_RCAL: case R_A2W_PLLH_PIX: case R_A2W_PLLB_ARM: update_channel_from_a2w(s, idx); break; + + case R_CM_GNRICCTL ... R_CM_SMIDIV: + case R_CM_TCNTCNT ... R_CM_VECDIV: + case R_CM_PULSECTL ... R_CM_PULSEDIV: + case R_CM_SDCCTL ... R_CM_ARMCTL: + case R_CM_AVEOCTL ... R_CM_EMMCDIV: + case R_CM_EMMC2CTL ... R_CM_EMMC2DIV: + update_mux_from_cm(s, idx); + break; } } =20 #undef CASE_PLL_A2W_REGS =20 @@ -394,10 +478,14 @@ static void cprman_reset(DeviceState *dev) =20 for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { device_cold_reset(DEVICE(&s->channels[i])); } =20 + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { + device_cold_reset(DEVICE(&s->clock_muxes[i])); + } + clock_update_hz(s->xosc, s->xosc_freq); } =20 static Clock *init_internal_clock(BCM2835CprmanState *s, const char *name) @@ -431,17 +519,69 @@ static void cprman_init(Object *obj) &s->channels[i], TYPE_CPRMAN_PLL_CHANNEL); set_pll_channel_init_info(s, &s->channels[i], i); } =20 + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { + char *alias; + + object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name, + &s->clock_muxes[i], + TYPE_CPRMAN_CLOCK_MUX); + set_clock_mux_init_info(s, &s->clock_muxes[i], i); + + /* Expose muxes output as CPRMAN outputs */ + alias =3D g_strdup_printf("%s-out", CLOCK_MUX_INIT_INFO[i].name); + qdev_alias_clock(DEVICE(&s->clock_muxes[i]), "out", DEVICE(obj), a= lias); + g_free(alias); + + } + s->xosc =3D init_internal_clock(s, "xosc"); + s->gnd =3D init_internal_clock(s, "gnd"); + + clock_set(s->gnd, 0); =20 memory_region_init_io(&s->iomem, obj, &cprman_ops, s, "bcm2835-cprman", 0x2000); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); } =20 +static void connect_mux_sources(BCM2835CprmanState *s, + CprmanClockMuxState *mux, + const CprmanPLLChannel *clk_mapping) +{ + size_t i; + Clock *td0 =3D s->clock_muxes[CPRMAN_CLOCK_TD0].out; + Clock *td1 =3D s->clock_muxes[CPRMAN_CLOCK_TD1].out; + + /* For sources from 0 to 3. Source 4 to 9 are mux specific */ + Clock * const CLK_SRC_MAPPING[] =3D { + [CPRMAN_CLOCK_SRC_GND] =3D s->gnd, + [CPRMAN_CLOCK_SRC_XOSC] =3D s->xosc, + [CPRMAN_CLOCK_SRC_TD0] =3D td0, + [CPRMAN_CLOCK_SRC_TD1] =3D td1, + }; + + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX_SRC; i++) { + CprmanPLLChannel mapping =3D clk_mapping[i]; + Clock *src; + + if (mapping =3D=3D CPRMAN_CLOCK_SRC_FORCE_GROUND) { + src =3D s->gnd; + } else if (mapping =3D=3D CPRMAN_CLOCK_SRC_DSI0HSCK) { + src =3D s->gnd; /* TODO */ + } else if (i < CPRMAN_CLOCK_SRC_PLLA) { + src =3D CLK_SRC_MAPPING[i]; + } else { + src =3D s->channels[mapping].out; + } + + clock_set_source(mux->srcs[i], src); + } +} + static void cprman_realize(DeviceState *dev, Error **errp) { BCM2835CprmanState *s =3D CPRMAN(dev); size_t i; =20 @@ -464,10 +604,20 @@ static void cprman_realize(DeviceState *dev, Error **= errp) =20 if (!qdev_realize(DEVICE(channel), NULL, errp)) { return; } } + + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { + CprmanClockMuxState *clock_mux =3D &s->clock_muxes[i]; + + connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mappi= ng); + + if (!qdev_realize(DEVICE(clock_mux), NULL, errp)) { + return; + } + } } =20 static const VMStateDescription cprman_vmstate =3D { .name =3D TYPE_BCM2835_CPRMAN, .version_id =3D 1, @@ -504,8 +654,9 @@ static const TypeInfo cprman_info =3D { static void cprman_register_types(void) { type_register_static(&cprman_info); type_register_static(&cprman_pll_info); type_register_static(&cprman_pll_channel_info); + type_register_static(&cprman_clock_mux_info); } =20 type_init(cprman_register_types); --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1601029369958730.1921584987175; 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bh=YOuCNbOOvSsStZNfbQT6hnxWhxzA58znlB/MmjZ2y5Y=; b=G2msWksehXz8+B/Ovvn/E5LRViL4pvyLW1sALYAcTxj/PZimXJtVomTYV9Soz80kz0jWpl 99USxdF3nWyh7ZQbcdPxoP0X6sPmeNkiDtJBAt2Iygu17s62FX2v7wMxk0TIJEhPc41y/e hhTG7Rhr5hI1f683WUkbsLJoYChY87cpEcAtM/xn5kR3rtJM/FYSmBVSwNCKoRszooNlBH 7mFE+lUzE4sRlAIvS0HGD6NOd+fkjASL3r48PXvcU4jhaRSu1Gt48zkzuW0FjopmBN4Gtn qd/rw6q2AWoOWVlVAdo38mcs4Xkw8LeU3eDLDJuqnFvlJcbNqnXGlzldoR0Luw== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 10/14] hw/misc/bcm2835_cprman: implement clock mux behaviour Date: Fri, 25 Sep 2020 12:17:27 +0200 Message-Id: <20200925101731.2159827-11-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YOuCNbOOvSsStZNfbQT6hnxWhxzA58znlB/MmjZ2y5Y=; b=bo65Qd9oZX9y5njzIvy/q/o7FobEiPuAX8wXitUrkGEQNS11R9Hf6bO8kxDEqAV3nAhRTB 6T2fnpDuWcg9KJZjMp8Y81UZKyK5A2aOaHs8QIhWhuDshZOlTe3wR5yAmH7IMBjmbdGm5d 29ejZSqzmVV4XrEInL/0SvDHmiRD/1O2hdiLuWYNEOsVkcxVE+7qdDggQBSKfGQaAbrYuX QDJ8HbLKkvhHR0eVZUBfLSyAdGi9vkFvsCusS+wrs4wqxIZ1e9VFjOBdI5TbabFNKQfDVu yqdHMAUbUW5c/ZSeKgXOsJ9sPo4cexS95VKaZtkw3rcg2Frgzy0WZtBoL+idPQ== ARC-Seal: i=1; s=pharaoh; d=lmichel.fr; t=1601029040; a=rsa-sha256; cv=none; b=GGDkSOnTdXoBFQ9yRk9piF5O1J/EAg7hbZwHfCxkXhQ+b1DbGL3OaiyGSm/2d0+YYkfAHJuSpw1JXVU6hlyXxHVnDYccaxmEqWf314fihXJp5mkS5meMyGmcDpUC0Ukx79Jo5uOHCbG1J1Cukf7T2Css9BhP6MBgfW34cbtNFkmKXAcK5MHnDaOdMpXeTdppk/0xFfYb50Iao6rARHpMqZkEkjBFNyCro5h7dDjDNw82qm+tYSa+78QR/Q2xKNfYSjWXVJz7yrLC0Ht0SDL5Hml8pjTf7NzGHdB8JXyHjBcVQrv/9juVniTOPhFjEhRytrj2Pi7ibyDCWkRbLpoGvw== ARC-Authentication-Results: i=1; pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" A clock mux can be configured to select one of its 10 sources through the cm_ctl register. It also embeds yet another clock divider, composed of an integer part and a fractionnal part. The number of bits of each part is mux dependant. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/misc/bcm2835_cprman.c | 43 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 42 insertions(+), 1 deletion(-) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 8df2db0fd9..75bc11939b 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -229,19 +229,60 @@ static const TypeInfo cprman_pll_channel_info =3D { }; =20 =20 /* clock mux */ =20 +static bool clock_mux_is_enabled(CprmanClockMuxState *mux) +{ + return FIELD_EX32(*mux->reg_cm, CM_CLOCKx_CTL, ENABLE); +} + static void clock_mux_update(CprmanClockMuxState *mux) { - clock_update(mux->out, 0); + uint64_t freq, div; + uint32_t src =3D FIELD_EX32(*mux->reg_cm, CM_CLOCKx_CTL, SRC); + bool enabled =3D clock_mux_is_enabled(mux); + + *mux->reg_cm =3D FIELD_DP32(*mux->reg_cm, CM_CLOCKx_CTL, BUSY, enabled= ); + + if (!enabled) { + clock_update(mux->out, 0); + return; + } + + freq =3D clock_get_hz(mux->srcs[src]); + + if (mux->int_bits =3D=3D 0 && mux->frac_bits =3D=3D 0) { + clock_update_hz(mux->out, freq); + return; + } + + /* + * The divider has an integer and a fractional part. The size of each = part + * varies with the muxes (int_bits and frac_bits). Both parts are + * concatenated, with the integer part always starting at bit 12. + */ + div =3D mux->reg_cm[1] >> (R_CM_CLOCKx_DIV_FRAC_LENGTH - mux->frac_bit= s); + div &=3D (1 << (mux->int_bits + mux->frac_bits)) - 1; + + freq =3D (freq << mux->frac_bits) / div; + + clock_update_hz(mux->out, freq); } =20 static void clock_mux_src_update(void *opaque) { CprmanClockMuxState **backref =3D opaque; CprmanClockMuxState *s =3D *backref; + CprmanClockMuxSource src =3D backref - s->backref; + uint32_t current_src; + + current_src =3D FIELD_EX32(*s->reg_cm, CM_CLOCKx_CTL, SRC); + + if (current_src !=3D src) { + return; + } =20 clock_mux_update(s); } =20 static void clock_mux_init(Object *obj) --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); 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a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MsNBR+iq9fdf+lKa2N77Xg9ZgMSlmTYx7Lrf4dgXr5M=; b=Z/yixsQk9LhChvn6Av25PKVNnCU2u7tFz3KPh7EOcnLhdElmL1kfIOWnpJL2YC+Le18X6R KBqwmEO+EJXlt11nAmINSnb/YxDTMwA+NLHrTpPJvmKi4NQ1QNJvE60lFqQRt8ymcy6BRC Hh0qEM/zT3EtAgDM9Lbo+CgWhdBukFNpvdAIqTt2xN6CKfQQgShNy0S1rrOkdNFEdmXNBB wSE/9HKiV7GWHm9hzXfpMISLrTLVb2MnPWBnQ1FluxEuDBz/rzaUR4jNMAkcBAg+4efW3m 5wMVjLglF0i1BvAPUB54FpCfF56z4cbTnhfOpRK8Lwg4pUspgE7KtoxAlDa1+g== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 11/14] hw/misc/bcm2835_cprman: add the DSI0HSCK multiplexer Date: Fri, 25 Sep 2020 12:17:28 +0200 Message-Id: <20200925101731.2159827-12-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; 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charset="utf-8" This simple mux sits between the PLL channels and the DSI0E and DSI0P clock muxes. This mux selects between PLLA-DSI0 and PLLD-DSI0 channel and outputs the selected signal to source number 4 of DSI0E/P clock muxes. It is controlled by the cm_dsi0hsck register. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/bcm2835_cprman.h | 15 +++++ include/hw/misc/bcm2835_cprman_internals.h | 6 ++ hw/misc/bcm2835_cprman.c | 78 +++++++++++++++++++++- 3 files changed, 98 insertions(+), 1 deletion(-) diff --git a/include/hw/misc/bcm2835_cprman.h b/include/hw/misc/bcm2835_cpr= man.h index c2a89e8e90..5555a299fc 100644 --- a/include/hw/misc/bcm2835_cprman.h +++ b/include/hw/misc/bcm2835_cprman.h @@ -171,20 +171,35 @@ typedef struct CprmanClockMuxState { * source number. */ struct CprmanClockMuxState *backref[CPRMAN_NUM_CLOCK_MUX_SRC]; } CprmanClockMuxState; =20 +typedef struct CprmanDsi0HsckMuxState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CprmanClockMux id; + + uint32_t *reg_cm; + + Clock *plla_in; + Clock *plld_in; + Clock *out; +} CprmanDsi0HsckMuxState; + struct BCM2835CprmanState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; =20 CprmanPLLState plls[CPRMAN_NUM_PLL]; CprmanPLLChannelState channels[CPRMAN_NUM_PLL_CHANNEL]; CprmanClockMuxState clock_muxes[CPRMAN_NUM_CLOCK_MUX]; + CprmanDsi0HsckMuxState dsi0hsck_mux; =20 uint32_t regs[CPRMAN_NUM_REGS]; uint32_t xosc_freq; =20 Clock *xosc; diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index a2b5a1aa50..ad07cf5276 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -13,17 +13,20 @@ #include "hw/misc/bcm2835_cprman.h" =20 #define TYPE_CPRMAN_PLL "bcm2835-cprman-pll" #define TYPE_CPRMAN_PLL_CHANNEL "bcm2835-cprman-pll-channel" #define TYPE_CPRMAN_CLOCK_MUX "bcm2835-cprman-clock-mux" +#define TYPE_CPRMAN_DSI0HSCK_MUX "bcm2835-cprman-dsi0hsck-mux" =20 DECLARE_INSTANCE_CHECKER(CprmanPLLState, CPRMAN_PLL, TYPE_CPRMAN_PLL) DECLARE_INSTANCE_CHECKER(CprmanPLLChannelState, CPRMAN_PLL_CHANNEL, TYPE_CPRMAN_PLL_CHANNEL) DECLARE_INSTANCE_CHECKER(CprmanClockMuxState, CPRMAN_CLOCK_MUX, TYPE_CPRMAN_CLOCK_MUX) +DECLARE_INSTANCE_CHECKER(CprmanDsi0HsckMuxState, CPRMAN_DSI0HSCK_MUX, + TYPE_CPRMAN_DSI0HSCK_MUX) =20 /* Register map */ =20 /* PLLs */ REG32(CM_PLLA, 0x104) @@ -221,10 +224,13 @@ REG32(CM_LOCK, 0x114) FIELD(CM_LOCK, FLOCKD, 11, 1) FIELD(CM_LOCK, FLOCKC, 10, 1) FIELD(CM_LOCK, FLOCKB, 9, 1) FIELD(CM_LOCK, FLOCKA, 8, 1) =20 +REG32(CM_DSI0HSCK, 0x120) + FIELD(CM_DSI0HSCK, SELPLLD, 0, 1) + /* * This field is common to all registers. Each register write value must m= atch * the CPRMAN_PASSWORD magic value in its 8 MSB. */ FIELD(CPRMAN, PASSWORD, 24, 8) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 75bc11939b..e576ab2642 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -327,10 +327,62 @@ static const TypeInfo cprman_clock_mux_info =3D { .class_init =3D clock_mux_class_init, .instance_init =3D clock_mux_init, }; =20 =20 +/* DSI0HSCK mux */ + +static void dsi0hsck_mux_update(CprmanDsi0HsckMuxState *s) +{ + bool src_is_plld =3D FIELD_EX32(*s->reg_cm, CM_DSI0HSCK, SELPLLD); + Clock *src =3D src_is_plld ? s->plld_in : s->plla_in; + + clock_update(s->out, clock_get(src)); +} + +static void dsi0hsck_mux_in_update(void *opaque) +{ + dsi0hsck_mux_update(CPRMAN_DSI0HSCK_MUX(opaque)); +} + +static void dsi0hsck_mux_init(Object *obj) +{ + CprmanDsi0HsckMuxState *s =3D CPRMAN_DSI0HSCK_MUX(obj); + DeviceState *dev =3D DEVICE(obj); + + s->plla_in =3D qdev_init_clock_in(dev, "plla-in", dsi0hsck_mux_in_upda= te, s); + s->plld_in =3D qdev_init_clock_in(dev, "plld-in", dsi0hsck_mux_in_upda= te, s); + s->out =3D qdev_init_clock_out(DEVICE(s), "out"); +} + +static const VMStateDescription dsi0hsck_mux_vmstate =3D { + .name =3D TYPE_CPRMAN_DSI0HSCK_MUX, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(plla_in, CprmanDsi0HsckMuxState), + VMSTATE_CLOCK(plld_in, CprmanDsi0HsckMuxState), + VMSTATE_END_OF_LIST() + } +}; + +static void dsi0hsck_mux_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &dsi0hsck_mux_vmstate; +} + +static const TypeInfo cprman_dsi0hsck_mux_info =3D { + .name =3D TYPE_CPRMAN_DSI0HSCK_MUX, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(CprmanDsi0HsckMuxState), + .class_init =3D dsi0hsck_mux_class_init, + .instance_init =3D dsi0hsck_mux_init, +}; + + /* CPRMAN "top level" model */ =20 static uint32_t get_cm_lock(const BCM2835CprmanState *s) { static const int CM_LOCK_MAPPING[] =3D { @@ -488,10 +540,14 @@ static void cprman_write(void *opaque, hwaddr offset, case R_CM_SDCCTL ... R_CM_ARMCTL: case R_CM_AVEOCTL ... R_CM_EMMCDIV: case R_CM_EMMC2CTL ... R_CM_EMMC2DIV: update_mux_from_cm(s, idx); break; + + case R_CM_DSI0HSCK: + dsi0hsck_mux_update(&s->dsi0hsck_mux); + break; } } =20 #undef CASE_PLL_A2W_REGS =20 @@ -519,10 +575,12 @@ static void cprman_reset(DeviceState *dev) =20 for (i =3D 0; i < CPRMAN_NUM_PLL_CHANNEL; i++) { device_cold_reset(DEVICE(&s->channels[i])); } =20 + device_cold_reset(DEVICE(&s->dsi0hsck_mux)); + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { device_cold_reset(DEVICE(&s->clock_muxes[i])); } =20 clock_update_hz(s->xosc, s->xosc_freq); @@ -560,10 +618,14 @@ static void cprman_init(Object *obj) &s->channels[i], TYPE_CPRMAN_PLL_CHANNEL); set_pll_channel_init_info(s, &s->channels[i], i); } =20 + object_initialize_child(obj, "dsi0hsck-mux", + &s->dsi0hsck_mux, TYPE_CPRMAN_DSI0HSCK_MUX); + s->dsi0hsck_mux.reg_cm =3D &s->regs[R_CM_DSI0HSCK]; + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { char *alias; =20 object_initialize_child(obj, CLOCK_MUX_INIT_INFO[i].name, &s->clock_muxes[i], @@ -608,11 +670,11 @@ static void connect_mux_sources(BCM2835CprmanState *s, Clock *src; =20 if (mapping =3D=3D CPRMAN_CLOCK_SRC_FORCE_GROUND) { src =3D s->gnd; } else if (mapping =3D=3D CPRMAN_CLOCK_SRC_DSI0HSCK) { - src =3D s->gnd; /* TODO */ + src =3D s->dsi0hsck_mux.out; } else if (i < CPRMAN_CLOCK_SRC_PLLA) { src =3D CLK_SRC_MAPPING[i]; } else { src =3D s->channels[mapping].out; } @@ -646,10 +708,23 @@ static void cprman_realize(DeviceState *dev, Error **= errp) if (!qdev_realize(DEVICE(channel), NULL, errp)) { return; } } =20 + { + CprmanDsi0HsckMuxState *dsi0hsck_mux =3D &s->dsi0hsck_mux; + + clock_set_source(dsi0hsck_mux->plla_in, + s->channels[CPRMAN_PLLA_CHANNEL_DSI0].out); + clock_set_source(dsi0hsck_mux->plld_in, + s->channels[CPRMAN_PLLD_CHANNEL_DSI0].out); + + if (!qdev_realize(DEVICE(dsi0hsck_mux), NULL, errp)) { + return; + } + } + for (i =3D 0; i < CPRMAN_NUM_CLOCK_MUX; i++) { CprmanClockMuxState *clock_mux =3D &s->clock_muxes[i]; =20 connect_mux_sources(s, clock_mux, CLOCK_MUX_INIT_INFO[i].src_mappi= ng); =20 @@ -696,8 +771,9 @@ static void cprman_register_types(void) { type_register_static(&cprman_info); type_register_static(&cprman_pll_info); type_register_static(&cprman_pll_channel_info); type_register_static(&cprman_clock_mux_info); + type_register_static(&cprman_dsi0hsck_mux_info); } =20 type_init(cprman_register_types); --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16010298289851010.2453425963984; Fri, 25 Sep 2020 03:30:28 -0700 (PDT) Received: from localhost ([::1]:49294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kLkzh-0007iE-I2 for importer@patchew.org; Fri, 25 Sep 2020 06:30:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42786) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknj-0001XP-Ia; Fri, 25 Sep 2020 06:18:04 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58244) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknd-0007SN-9R; Fri, 25 Sep 2020 06:18:02 -0400 Received: from sekoia-pc.bar.greensocs.com (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id D7558C60F24; Fri, 25 Sep 2020 10:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XYmTD4UkWAFnlkcU34EMX40lMfSmz6vUyQ7STKLwesk=; b=DHi72S62IkVE1v4kGD8A1tHQY8kC7rYG6BbaYGUK6rtKRvXH4iBap0uNnKVJsl1uyGzsqj Ji8eZXalGWg+gjsxDlRSlI3BWz9qZdVw6+1X/C3nxSKa7UwF/bbOpN88fZg8ZiLisJljku hpmwb68xQn6jFSSWbuiDPb0GR88AH00DHAXBgwi8OQo2DNgfD8FsKmhIil0FHRkxkogKm1 vLF0wcr5FzIFOp2dc8ehRXTWbfkbtcokSbwkDDDhXWLEoqGY9hSQK2TRoBSDRH6OGTV9Ue nqVdPVeLjWxZPm8ae9aU1r0Qv642srci7tzhZeZbUEuijqdhm7KHzGgOgOYVzg== From: Luc Michel To: qemu-devel@nongnu.org Subject: [PATCH 12/14] hw/misc/bcm2835_cprman: add sane reset values to the registers Date: Fri, 25 Sep 2020 12:17:29 +0200 Message-Id: <20200925101731.2159827-13-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; 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pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Those reset values have been extracted from a Raspberry Pi 3 model B v1.2, using the 2020-08-20 version of raspios. The dump was done using the debugfs interface of the cprman driver in Linux (under '/sys/kernel/debug/clk'). Each exposed clock tree stage (PLLs, channels and muxes) can be observed by reading the 'regdump' file (e.g. 'plla/regdump'). Those values are set by the Raspberry Pi firmware at boot time (Linux expects them to be set when it boots up). Some stages are not exposed by the Linux driver (e.g. the PLL B). For those, the reset values are unknown and left to 0 which implies a disabled output. Once booted in QEMU, the final clock tree is very similar to the one visible on real hardware. The differences come from some unimplemented devices for which the driver simply disable the corresponding clock. Signed-off-by: Luc Michel Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/misc/bcm2835_cprman_internals.h | 269 +++++++++++++++++++++ hw/misc/bcm2835_cprman.c | 31 +++ 2 files changed, 300 insertions(+) diff --git a/include/hw/misc/bcm2835_cprman_internals.h b/include/hw/misc/b= cm2835_cprman_internals.h index ad07cf5276..f5e168ccf9 100644 --- a/include/hw/misc/bcm2835_cprman_internals.h +++ b/include/hw/misc/bcm2835_cprman_internals.h @@ -744,6 +744,275 @@ static inline void set_clock_mux_init_info(BCM2835Cpr= manState *s, mux->reg_cm =3D &s->regs[CLOCK_MUX_INIT_INFO[id].cm_offset]; mux->int_bits =3D CLOCK_MUX_INIT_INFO[id].int_bits; mux->frac_bits =3D CLOCK_MUX_INIT_INFO[id].frac_bits; } =20 + +/* + * Object reset info + * Those values have been dumped from a Raspberry Pi 3 Model B v1.2 using = the + * clk debugfs interface in Linux. + */ +typedef struct PLLResetInfo { + uint32_t cm; + uint32_t a2w_ctrl; + uint32_t a2w_ana[4]; + uint32_t a2w_frac; +} PLLResetInfo; + +static const PLLResetInfo PLL_RESET_INFO[] =3D { + [CPRMAN_PLLA] =3D { + .cm =3D 0x0000008a, + .a2w_ctrl =3D 0x0002103a, + .a2w_frac =3D 0x00098000, + .a2w_ana =3D { 0x00000000, 0x00144000, 0x00000000, 0x00000100 } + }, + + [CPRMAN_PLLC] =3D { + .cm =3D 0x00000228, + .a2w_ctrl =3D 0x0002103e, + .a2w_frac =3D 0x00080000, + .a2w_ana =3D { 0x00000000, 0x00144000, 0x00000000, 0x00000100 } + }, + + [CPRMAN_PLLD] =3D { + .cm =3D 0x0000020a, + .a2w_ctrl =3D 0x00021034, + .a2w_frac =3D 0x00015556, + .a2w_ana =3D { 0x00000000, 0x00144000, 0x00000000, 0x00000100 } + }, + + [CPRMAN_PLLH] =3D { + .cm =3D 0x00000000, + .a2w_ctrl =3D 0x0002102d, + .a2w_frac =3D 0x00000000, + .a2w_ana =3D { 0x00900000, 0x0000000c, 0x00000000, 0x00000000 } + }, + + [CPRMAN_PLLB] =3D { + /* unknown */ + .cm =3D 0x00000000, + .a2w_ctrl =3D 0x00000000, + .a2w_frac =3D 0x00000000, + .a2w_ana =3D { 0x00000000, 0x00000000, 0x00000000, 0x00000000 } + } +}; + +typedef struct PLLChannelResetInfo { + /* + * Even though a PLL channel has a CM register, it shares it with its + * parent PLL. The parent already takes care of the reset value. + */ + uint32_t a2w_ctrl; +} PLLChannelResetInfo; + +static const PLLChannelResetInfo PLL_CHANNEL_RESET_INFO[] =3D { + [CPRMAN_PLLA_CHANNEL_DSI0] =3D { .a2w_ctrl =3D 0x00000100 }, + [CPRMAN_PLLA_CHANNEL_CORE] =3D { .a2w_ctrl =3D 0x00000003 }, + [CPRMAN_PLLA_CHANNEL_PER] =3D { .a2w_ctrl =3D 0x00000000 }, /* unknown= */ + [CPRMAN_PLLA_CHANNEL_CCP2] =3D { .a2w_ctrl =3D 0x00000100 }, + + [CPRMAN_PLLC_CHANNEL_CORE2] =3D { .a2w_ctrl =3D 0x00000100 }, + [CPRMAN_PLLC_CHANNEL_CORE1] =3D { .a2w_ctrl =3D 0x00000100 }, + [CPRMAN_PLLC_CHANNEL_PER] =3D { .a2w_ctrl =3D 0x00000002 }, + [CPRMAN_PLLC_CHANNEL_CORE0] =3D { .a2w_ctrl =3D 0x00000002 }, + + [CPRMAN_PLLD_CHANNEL_DSI0] =3D { .a2w_ctrl =3D 0x00000100 }, + [CPRMAN_PLLD_CHANNEL_CORE] =3D { .a2w_ctrl =3D 0x00000004 }, + [CPRMAN_PLLD_CHANNEL_PER] =3D { .a2w_ctrl =3D 0x00000004 }, + [CPRMAN_PLLD_CHANNEL_DSI1] =3D { .a2w_ctrl =3D 0x00000100 }, + + [CPRMAN_PLLH_CHANNEL_AUX] =3D { .a2w_ctrl =3D 0x00000004 }, + [CPRMAN_PLLH_CHANNEL_RCAL] =3D { .a2w_ctrl =3D 0x00000000 }, + [CPRMAN_PLLH_CHANNEL_PIX] =3D { .a2w_ctrl =3D 0x00000000 }, + + [CPRMAN_PLLB_CHANNEL_ARM] =3D { .a2w_ctrl =3D 0x00000000 }, /* unknown= */ +}; + +typedef struct ClockMuxResetInfo { + uint32_t cm_ctrl; + uint32_t cm_div; +} ClockMuxResetInfo; + +static const ClockMuxResetInfo CLOCK_MUX_RESET_INFO[] =3D { + [CPRMAN_CLOCK_GNRIC] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_VPU] =3D { + .cm_ctrl =3D 0x00000245, + .cm_div =3D 0x00003000, + }, + + [CPRMAN_CLOCK_SYS] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_PERIA] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_PERII] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_H264] =3D { + .cm_ctrl =3D 0x00000244, + .cm_div =3D 0x00003000, + }, + + [CPRMAN_CLOCK_ISP] =3D { + .cm_ctrl =3D 0x00000244, + .cm_div =3D 0x00003000, + }, + + [CPRMAN_CLOCK_V3D] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_CAM0] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_CAM1] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_CCP2] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_DSI0E] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_DSI0P] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_DPI] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_GP0] =3D { + .cm_ctrl =3D 0x00000200, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_GP1] =3D { + .cm_ctrl =3D 0x00000096, + .cm_div =3D 0x00014000, + }, + + [CPRMAN_CLOCK_GP2] =3D { + .cm_ctrl =3D 0x00000291, + .cm_div =3D 0x00249f00, + }, + + [CPRMAN_CLOCK_HSM] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_OTP] =3D { + .cm_ctrl =3D 0x00000091, + .cm_div =3D 0x00004000, + }, + + [CPRMAN_CLOCK_PCM] =3D { + .cm_ctrl =3D 0x00000200, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_PWM] =3D { + .cm_ctrl =3D 0x00000200, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_SLIM] =3D { + .cm_ctrl =3D 0x00000200, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_SMI] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_TEC] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_TD0] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_TD1] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_TSENS] =3D { + .cm_ctrl =3D 0x00000091, + .cm_div =3D 0x0000a000, + }, + + [CPRMAN_CLOCK_TIMER] =3D { + .cm_ctrl =3D 0x00000291, + .cm_div =3D 0x00013333, + }, + + [CPRMAN_CLOCK_UART] =3D { + .cm_ctrl =3D 0x00000296, + .cm_div =3D 0x0000a6ab, + }, + + [CPRMAN_CLOCK_VEC] =3D { + .cm_ctrl =3D 0x00000097, + .cm_div =3D 0x00002000, + }, + + [CPRMAN_CLOCK_PULSE] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_SDC] =3D { + .cm_ctrl =3D 0x00004006, + .cm_div =3D 0x00003000, + }, + + [CPRMAN_CLOCK_ARM] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, + + [CPRMAN_CLOCK_AVEO] =3D { + .cm_ctrl =3D 0x00000000, + .cm_div =3D 0x00000000, + }, + + [CPRMAN_CLOCK_EMMC] =3D { + .cm_ctrl =3D 0x00000295, + .cm_div =3D 0x00006000, + }, + + [CPRMAN_CLOCK_EMMC2] =3D { + .cm_ctrl =3D 0, /* unknown */ + .cm_div =3D 0 + }, +}; + #endif diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index e576ab2642..a8b54cccdb 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -51,10 +51,21 @@ #include "hw/misc/bcm2835_cprman_internals.h" #include "trace.h" =20 /* PLL */ =20 +static void pll_reset(DeviceState *dev) +{ + CprmanPLLState *s =3D CPRMAN_PLL(dev); + const PLLResetInfo *info =3D &PLL_RESET_INFO[s->id]; + + *s->reg_cm =3D info->cm; + *s->reg_a2w_ctrl =3D info->a2w_ctrl; + memcpy(s->reg_a2w_ana, info->a2w_ana, sizeof(info->a2w_ana)); + *s->reg_a2w_frac =3D info->a2w_frac; +} + static bool pll_is_locked(const CprmanPLLState *pll) { return !FIELD_EX32(*pll->reg_a2w_ctrl, A2W_PLLx_CTRL, PWRDN) && !FIELD_EX32(*pll->reg_cm, CM_PLLx, ANARST); } @@ -121,10 +132,11 @@ static const VMStateDescription pll_vmstate =3D { =20 static void pll_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D pll_reset; dc->vmsd =3D &pll_vmstate; } =20 static const TypeInfo cprman_pll_info =3D { .name =3D TYPE_CPRMAN_PLL, @@ -135,10 +147,18 @@ static const TypeInfo cprman_pll_info =3D { }; =20 =20 /* PLL channel */ =20 +static void pll_channel_reset(DeviceState *dev) +{ + CprmanPLLChannelState *s =3D CPRMAN_PLL_CHANNEL(dev); + const PLLChannelResetInfo *info =3D &PLL_CHANNEL_RESET_INFO[s->id]; + + *s->reg_a2w_ctrl =3D info->a2w_ctrl; +} + static bool pll_channel_is_enabled(CprmanPLLChannelState *channel) { /* * XXX I'm not sure of the purpose of the LOAD field. The Linux driver= does * not set it when enabling the channel, but does clear it when disabl= ing @@ -215,10 +235,11 @@ static const VMStateDescription pll_channel_vmstate = =3D { =20 static void pll_channel_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D pll_channel_reset; dc->vmsd =3D &pll_channel_vmstate; } =20 static const TypeInfo cprman_pll_channel_info =3D { .name =3D TYPE_CPRMAN_PLL_CHANNEL, @@ -283,10 +304,19 @@ static void clock_mux_src_update(void *opaque) } =20 clock_mux_update(s); } =20 +static void clock_mux_reset(DeviceState *dev) +{ + CprmanClockMuxState *clock =3D CPRMAN_CLOCK_MUX(dev); + const ClockMuxResetInfo *info =3D &CLOCK_MUX_RESET_INFO[clock->id]; + + clock->reg_cm[0] =3D info->cm_ctrl; + clock->reg_cm[1] =3D info->cm_div; +} + static void clock_mux_init(Object *obj) { CprmanClockMuxState *s =3D CPRMAN_CLOCK_MUX(obj); size_t i; =20 @@ -315,10 +345,11 @@ static const VMStateDescription clock_mux_vmstate =3D= { =20 static void clock_mux_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + dc->reset =3D clock_mux_reset; dc->vmsd =3D &clock_mux_vmstate; } =20 static const TypeInfo cprman_clock_mux_info =3D { .name =3D TYPE_CPRMAN_CLOCK_MUX, --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1601029500375198.58533855037842; Fri, 25 Sep 2020 03:25:00 -0700 (PDT) Received: from localhost ([::1]:36090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kLkuQ-0001tH-Uv for importer@patchew.org; Fri, 25 Sep 2020 06:24:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknm-0001Z8-4l; Fri, 25 Sep 2020 06:18:06 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58262) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknh-0007So-TJ; Fri, 25 Sep 2020 06:18:05 -0400 Received: from sekoia-pc.bar.greensocs.com (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id EBF81C60F25; Fri, 25 Sep 2020 10:17:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029040; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Jzk0uP9k3MS5cnLaH5qrGE/fnKTXANTCV6K+Nith/Go=; b=hfb9RzTP6dXBiznw5KlW87C53QFgpKuyurFMogcw5A/Z2+gOsWWxdJj4lq1H9IXIm7XtDj Ze7oGFn2YoThG2R0mJqc3CDLxkl0qSS575WHOVQ4WcHDBqD+STFCtn8c56y1bLGegu5yf4 CaxOw6SzzjqP5nR6U/vqzuP+zA6PlUHqGXy8uyu4CCmJNKbr2CB+GnsrFyBjxuXQAcIlMD RMTarrPtfFPgIEb9b7B1CKRUlzS3+Nuw65nO4uXiFUkBeUFUNV0tSKFmejCgcn6dKnEJwV kNh1+f1FuzgYMLbRZMMP+RmU7rS0NEGbey+DSXCmUuBv13CbMueF3H8cw2Rf6g== From: Luc Michel To: qemu-devel@nongnu.org Subject: [RFC PATCH 13/14] hw/char/pl011: add a clock input Date: Fri, 25 Sep 2020 12:17:30 +0200 Message-Id: <20200925101731.2159827-14-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; 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pharaoh.lmichel.fr Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=149.202.28.74; envelope-from=luc@lmichel.fr; helo=pharaoh.lmichel.fr X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/25 06:17:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Luc Michel , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add a clock input to the PL011 UART so we can compute the current baud rate and trace it. This is intended for developers who wish to use QEMU to e.g. debug their firmware or to figure out the baud rate configured by an unknown/closed source binary. Signed-off-by: Luc Michel Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/char/pl011.h | 1 + hw/char/pl011.c | 45 +++++++++++++++++++++++++++++++++++++++++ hw/char/trace-events | 1 + 3 files changed, 47 insertions(+) diff --git a/include/hw/char/pl011.h b/include/hw/char/pl011.h index a91ea50e11..33e5e5317b 100644 --- a/include/hw/char/pl011.h +++ b/include/hw/char/pl011.h @@ -47,10 +47,11 @@ struct PL011State { int read_pos; int read_count; int read_trigger; CharBackend chr; qemu_irq irq[6]; + Clock *clk; const unsigned char *id; }; =20 static inline DeviceState *pl011_create(hwaddr addr, qemu_irq irq, diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 13e784f9d9..ede16c781c 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -20,10 +20,11 @@ =20 #include "qemu/osdep.h" #include "hw/char/pl011.h" #include "hw/irq.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "migration/vmstate.h" #include "chardev/char-fe.h" #include "qemu/log.h" #include "qemu/module.h" #include "trace.h" @@ -167,10 +168,29 @@ static void pl011_set_read_trigger(PL011State *s) else #endif s->read_trigger =3D 1; } =20 +static unsigned int pl011_get_baudrate(const PL011State *s) +{ + uint64_t clk; + + if (s->fbrd =3D=3D 0) { + return 0; + } + + clk =3D clock_get_hz(s->clk); + return (clk / ((s->ibrd << 6) + s->fbrd)) << 2; +} + +static void pl011_trace_baudrate_change(const PL011State *s) +{ + trace_pl011_baudrate_change(pl011_get_baudrate(s), + clock_get_hz(s->clk), + s->ibrd, s->fbrd); +} + static void pl011_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { PL011State *s =3D (PL011State *)opaque; unsigned char ch; @@ -196,13 +216,15 @@ static void pl011_write(void *opaque, hwaddr offset, case 8: /* UARTUARTILPR */ s->ilpr =3D value; break; case 9: /* UARTIBRD */ s->ibrd =3D value; + pl011_trace_baudrate_change(s); break; case 10: /* UARTFBRD */ s->fbrd =3D value; + pl011_trace_baudrate_change(s); break; case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ if ((s->lcr ^ value) & 0x10) { s->read_count =3D 0; @@ -284,16 +306,33 @@ static void pl011_event(void *opaque, QEMUChrEvent ev= ent) { if (event =3D=3D CHR_EVENT_BREAK) pl011_put_fifo(opaque, 0x400); } =20 +static void pl011_clock_update(void *opaque) +{ + PL011State *s =3D PL011(opaque); + + pl011_trace_baudrate_change(s); +} + static const MemoryRegionOps pl011_ops =3D { .read =3D pl011_read, .write =3D pl011_write, .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static const VMStateDescription vmstate_pl011_clock =3D { + .name =3D "pl011/clock", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_CLOCK(clk, PL011State), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_pl011 =3D { .name =3D "pl011", .version_id =3D 2, .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { @@ -312,10 +351,14 @@ static const VMStateDescription vmstate_pl011 =3D { VMSTATE_UINT32(ifl, PL011State), VMSTATE_INT32(read_pos, PL011State), VMSTATE_INT32(read_count, PL011State), VMSTATE_INT32(read_trigger, PL011State), VMSTATE_END_OF_LIST() + }, + .subsections =3D (const VMStateDescription * []) { + &vmstate_pl011_clock, + NULL } }; =20 static Property pl011_properties[] =3D { DEFINE_PROP_CHR("chardev", PL011State, chr), @@ -332,10 +375,12 @@ static void pl011_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); for (i =3D 0; i < ARRAY_SIZE(s->irq); i++) { sysbus_init_irq(sbd, &s->irq[i]); } =20 + s->clk =3D qdev_init_clock_in(DEVICE(obj), "clk", pl011_clock_update, = s); + s->read_trigger =3D 1; s->ifl =3D 0x12; s->cr =3D 0x300; s->flags =3D 0x90; =20 diff --git a/hw/char/trace-events b/hw/char/trace-events index 2442a9f7d5..cc1f0065ac 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -62,10 +62,11 @@ pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x = value 0x%08x" pl011_read_fifo(int read_count) "FIFO read, read_count now %d" pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_co= unt %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %= d" pl011_put_fifo_full(void) "FIFO now full, RXFF set" +pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd= , uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", f= brd: %" PRIu32 ")" =20 # cmsdk-apb-uart.c cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK = APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" cmsdk_apb_uart_write(uint64_t offset, uint64_t data, unsigned size) "CMSDK= APB UART write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" cmsdk_apb_uart_reset(void) "CMSDK APB UART: reset" --=20 2.28.0 From nobody Tue May 14 16:05:49 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (Bad Signature); dmarc=fail(p=none dis=none) header.from=lmichel.fr Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160102967646978.01932259549756; Fri, 25 Sep 2020 03:27:56 -0700 (PDT) Received: from localhost ([::1]:42364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kLkxG-0004kB-S5 for importer@patchew.org; Fri, 25 Sep 2020 06:27:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknk-0001Yd-TO; Fri, 25 Sep 2020 06:18:06 -0400 Received: from pharaoh.lmichel.fr ([149.202.28.74]:58264) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kLknh-0007Sp-TQ; Fri, 25 Sep 2020 06:18:04 -0400 Received: from sekoia-pc.bar.greensocs.com (sekoia-pc.home.lmichel.fr [192.168.61.100]) by pharaoh.lmichel.fr (Postfix) with ESMTPS id 08C2BC61424; Fri, 25 Sep 2020 10:17:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=lmichel.fr; s=pharaoh; t=1601029041; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nYIO6oVFxUZV1TH9x+9OCm3cGZXkpXFo/VqRcUn44+U=; b=DW5g0qjJIUMvhhgTBWSkRp+9YOyVNrwX/TP5EYfA9pPjQkKw4xKeLN3MSNEh5ScPFyHrsz NGZkXToXVrQ4VgC6E6iKmkeB8/EqM3i4iydCSaODOPMDqu1xtd0yAgQ+caGy11LnD2Bgjy zE+guOKG/BER9sTPEXjFevFEIs6z0PPPr2tgmwBI2xvGjMZQzDMx5gemd96iAoTjNmTw7a hUlh5VdfCNUMm3sTMOStOyz6Gbsiv+AonGiJzSVMg78KEMq1FWy5UzMp1+UUGCeCkbsCwa e+euD6wI4Cq3DYAsMV1KHVkLxW43dB2B38Szm2apup60oYERn38NACX+1KH52w== From: Luc Michel To: qemu-devel@nongnu.org Subject: [RFC PATCH 14/14] hw/arm/bcm2835_peripherals: connect the UART clock Date: Fri, 25 Sep 2020 12:17:31 +0200 Message-Id: <20200925101731.2159827-15-luc@lmichel.fr> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200925101731.2159827-1-luc@lmichel.fr> References: <20200925101731.2159827-1-luc@lmichel.fr> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable ARC-Message-Signature: i=1; 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charset="utf-8" Connect the 'uart-out' clock from the cprman to the PL011 instance. Signed-off-by: Luc Michel Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/bcm2835_peripherals.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 958aadeeb9..9e4e85c3ad 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -167,10 +167,12 @@ static void bcm2835_peripherals_realize(DeviceState *= dev, Error **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->cprman), errp)) { return; } memory_region_add_subregion(&s->peri_mr, CPRMAN_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cprman), 0)); + qdev_connect_clock_in(DEVICE(&s->uart0), "clk", + qdev_get_clock_out(DEVICE(&s->cprman), "uart-out= ")); =20 memory_region_add_subregion(&s->peri_mr, ARMCTRL_IC_OFFSET, sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->ic), 0)); sysbus_pass_irq(SYS_BUS_DEVICE(s), SYS_BUS_DEVICE(&s->ic)); =20 --=20 2.28.0