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bh=IL7nzAh7Mf9HR3Z9mYJS5y5wKlSwZthpUxqWFbQmTzM=; b=Wjmt9wshxiziH9BGdSn73ClOTUWSstot8pjdNE+bANX60oM9G8yPXb4UMbgpPN0oomGFXx A0aLgpPzvPfZyprNFXMNktijJvXaYVU/U79i/E5kv1iRRyiKwTjNxiMLE2FVfKgkyeNnHF 5d9a1+YPujmGVZEzaWHmBoqEsBXGiuo= X-MC-Unique: 3SGnW4NzOBiEyHxyYYUmfQ-1 From: Julia Suvorova To: qemu-devel@nongnu.org Subject: [RFC PATCH v3 3/7] hw/pci/pcie: Do not initialize slot capability if acpihp is used Date: Thu, 24 Sep 2020 09:00:09 +0200 Message-Id: <20200924070013.165026-4-jusual@redhat.com> In-Reply-To: <20200924070013.165026-1-jusual@redhat.com> References: <20200924070013.165026-1-jusual@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jusual@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=jusual@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/22 23:02:20 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -32 X-Spam_score: -3.3 X-Spam_bar: --- X-Spam_report: (-3.3 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1.228, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ani Sinha , Igor Mammedov , Julia Suvorova , "Michael S. Tsirkin" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Instead of changing the hot-plug type in _OSC register, do not initialize the slot capability or set the 'Slot Implemented' flag. This way guest will choose ACPI hot-plug if it is preferred and leave the option to use SHPC with pcie-pci-bridge. Signed-off-by: Julia Suvorova --- hw/i386/acpi-build.h | 2 ++ hw/i386/acpi-build.c | 2 +- hw/pci/pcie.c | 16 ++++++++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.h b/hw/i386/acpi-build.h index 487ec7710f..4c5bfb3d0b 100644 --- a/hw/i386/acpi-build.h +++ b/hw/i386/acpi-build.h @@ -11,4 +11,6 @@ extern const struct AcpiGenericAddress x86_nvdimm_acpi_ds= mio; =20 void acpi_setup(void); =20 +Object *object_resolve_type_unambiguous(const char *typename); + #endif diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index cf503b16af..b7811a8912 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -174,7 +174,7 @@ static void init_common_fadt_data(MachineState *ms, Obj= ect *o, *data =3D fadt; } =20 -static Object *object_resolve_type_unambiguous(const char *typename) +Object *object_resolve_type_unambiguous(const char *typename) { bool ambig; Object *o =3D object_resolve_path_type("", typename, &ambig); diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 5b48bae0f6..c1a082e8b9 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -27,6 +27,8 @@ #include "hw/pci/pci_bus.h" #include "hw/pci/pcie_regs.h" #include "hw/pci/pcie_port.h" +#include "hw/i386/ich9.h" +#include "hw/i386/acpi-build.h" #include "qemu/range.h" =20 //#define DEBUG_PCIE @@ -515,12 +517,26 @@ void pcie_cap_slot_unplug_request_cb(HotplugHandler *= hotplug_dev, pcie_cap_slot_push_attention_button(hotplug_pdev); } =20 +static bool acpi_pcihp_enabled(void) +{ + Object *lpc =3D object_resolve_type_unambiguous(TYPE_ICH9_LPC_DEVICE); + + return lpc && + object_property_get_bool(lpc, "acpi-pci-hotplug-with-bridge-sup= port", + NULL); + +} + /* pci express slot for pci express root/downstream port PCI express capability slot registers */ void pcie_cap_slot_init(PCIDevice *dev, PCIESlot *s) { uint32_t pos =3D dev->exp.exp_cap; =20 + if (acpi_pcihp_enabled()) { + return; + } + pci_word_test_and_set_mask(dev->config + pos + PCI_EXP_FLAGS, PCI_EXP_FLAGS_SLOT); =20 --=20 2.25.4