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[83.57.170.65]) by smtp.gmail.com with ESMTPSA id u66sm3634947wme.12.2020.09.22.01.38.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2020 01:38:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1600763931; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0oUMbvSMybNmnNxDNxqBQV+vJ3XelXwsh3Q4bryO1QA=; b=PuBkZnwEOtIC54iGOkWVdyelIkw6aSd92x2vEKSv5TVoA78SUdKVHJ1eOOzaqIcVmwoeea yX8OYtHVBKDvDL7Jp/hNkGGrlFFINCyKHy36OgpVbXEIvNF7FqNfOC/giw+JmRphmEnA3/ sTBL7Qj1weaBGvVxQJd44vYG1X/Rh/M= X-MC-Unique: QlI0hzYyN3WmP-6OxjQbig-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0oUMbvSMybNmnNxDNxqBQV+vJ3XelXwsh3Q4bryO1QA=; b=fRY3dvqp2DgWbs9GJJTknNYGT5iGvVmqBsRPpp9LiqQkNpsuSoIsMwOxNUgHRydVV/ G810nOH+s7JpcCtOHmKuQqFLwCOmk5iBuTgOYhrMbGBMXQ/cxhIJr94Ieh6ZzfkTZbcJ pjI4lUPk4rVtxDVrqCyPVOgedhhRt4oeJQtGS4xPCS28MQcZ4CGjRMhqdk9Cky15i3GU pK3NAn0ZPzc/3SIG1BVmogcb7VIcTwYVR3mS5teqztBJqWC0rzQdFvlDAbo91xi7H8Gs cNVzGwjOI/vkXQGkr0yM9hMF6QYNh8Tf3cg9WwT+0la4qPPW1qvJ3rOfKxAl7D+QyNQF URZg== X-Gm-Message-State: AOAM53189AfoTNrs+t7tQIKiqEXZb/Eha4J/WB6AC0Rb1ekygB8+6+fG auDGVZRnLz4kWGFovf4N/0jNL9EaHaHQT3UNAymUPsXatnJ452vYWYw1qUbJRUZKhJvwuRag5jl Wsm5PBmwJ8RClBA== X-Received: by 2002:a5d:4d51:: with SMTP id a17mr4037242wru.248.1600763924457; Tue, 22 Sep 2020 01:38:44 -0700 (PDT) X-Google-Smtp-Source: ABdhPJyoT63a4O62yTIZCWlOOnvcKmJ+6l9YijfzUd62oqIbvbXG5RnJkhxDcC4oNk4iulDEYZn9Hg== X-Received: by 2002:a5d:4d51:: with SMTP id a17mr4037224wru.248.1600763924289; Tue, 22 Sep 2020 01:38:44 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Stefan Hajnoczi Cc: Fam Zheng , Max Reitz , qemu-block@nongnu.org, Kevin Wolf , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 4/6] block/nvme: Drop NVMeRegs structure, directly use NvmeBar Date: Tue, 22 Sep 2020 10:38:19 +0200 Message-Id: <20200922083821.578519-5-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200922083821.578519-1-philmd@redhat.com> References: <20200922083821.578519-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) NVMeRegs only contains NvmeBar. Simplify the code by using NvmeBar directly. This triggers a checkpatch.pl error: ERROR: Use of volatile is usually wrong, please add a comment #30: FILE: block/nvme.c:691: + volatile NvmeBar *regs; This is a false positive as in our case we are using I/O registers, so the 'volatile' use is justified. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index e517c7539ff..bd82990b66c 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -81,11 +81,6 @@ typedef struct { QEMUBH *completion_bh; } NVMeQueuePair; =20 -/* Memory mapped registers */ -typedef volatile struct { - NvmeBar ctrl; -} NVMeRegs; - #define INDEX_ADMIN 0 #define INDEX_IO(n) (1 + n) =20 @@ -694,7 +689,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, uint64_t timeout_ms; uint64_t deadline, now; Error *local_err =3D NULL; - NVMeRegs *regs; + volatile NvmeBar *regs =3D NULL; =20 qemu_co_mutex_init(&s->dma_map_lock); qemu_co_queue_init(&s->dma_flush_queue); @@ -722,7 +717,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, /* Perform initialize sequence as described in NVMe spec "7.6.1 * Initialization". */ =20 - cap =3D le64_to_cpu(regs->ctrl.cap); + cap =3D le64_to_cpu(regs->cap); if (!(cap & (1ULL << 37))) { error_setg(errp, "Device doesn't support NVMe command set"); ret =3D -EINVAL; @@ -735,10 +730,10 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, timeout_ms =3D MIN(500 * ((cap >> 24) & 0xFF), 30000); =20 /* Reset device to get a clean state. */ - regs->ctrl.cc =3D cpu_to_le32(le32_to_cpu(regs->ctrl.cc) & 0xFE); + regs->cc =3D cpu_to_le32(le32_to_cpu(regs->cc) & 0xFE); /* Wait for CSTS.RDY =3D 0. */ deadline =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCA= LE_MS; - while (le32_to_cpu(regs->ctrl.csts) & 0x1) { + while (le32_to_cpu(regs->csts) & 0x1) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to reset (%" PRId64 " ms)", @@ -766,18 +761,18 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); - regs->ctrl.aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SI= ZE); - regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); - regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); + regs->aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE); + regs->asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); + regs->acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); =20 /* After setting up all control registers we can enable device now. */ - regs->ctrl.cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | + regs->cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 0x1); /* Wait for CSTS.RDY =3D 1. */ now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); deadline =3D now + timeout_ms * 1000000; - while (!(le32_to_cpu(regs->ctrl.csts) & 0x1)) { + while (!(le32_to_cpu(regs->csts) & 0x1)) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to start (%" PRId64 " ms)", --=20 2.26.2