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[83.57.170.65]) by smtp.gmail.com with ESMTPSA id c4sm22477296wrp.85.2020.09.21.09.30.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 21 Sep 2020 09:30:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1600705811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w3VSohO81qj1Qy9GMUYU8rCdXvyUaEcpLhj6tPxRG5I=; b=FEfiBlN+hmGU9ysVWNegYuWrvEmJ23wMUtkZ7OOQTLU0oa/ghSu1GKE+oOUt9tnpeDQvxF ujGGXdtYBE6tmpUO5DUFSPAks832ErtUEV03o8kPgIFHIDcLnv0Mcpb+C7Gfw2hd64z2/E ncPrVjRJnmtfXk3tbCOheHYO4V3i4Qw= X-MC-Unique: QTFAsNPcNravg2qHlIzAEA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w3VSohO81qj1Qy9GMUYU8rCdXvyUaEcpLhj6tPxRG5I=; b=njyYYkzCIVvJGiRKyHGAVdmkv3LdPKWYcYVqghWfSFHbFV0HrCKg5mxcA3xAG0p5ZK rdlR9uwUOqljJYsZeBMr6sgn5BIIL/N+QY2ovcWo6Keq78R5aScvuT4sidrrRAQGFhP8 X0DcYMYKvJjz8W5pPRmxTDbkwpj0RNc79RvuFGbnCSneFTkycdNDDynEksusahKzItaO Ohn4vgXP73pLQmLzdCT2NZsg69YIGAHSOEARvgd5ADI9isvuGwsztH6bGolGaZymTBCG VEeG1mAbKxFeXNXT23Mcd9QW+JfFt8uyaMakmurLClqZsCOUkOcuSDZTnA4ff082bmvr zkDg== X-Gm-Message-State: AOAM533F9o4xl4QPVtJCmBiDRDWkOOTT9TWGjtHAnyGEKBEGDYLw5APP SCoLxHbWiCx3Ys9s2y3QLnibnupFDEZ2VpKhmhritZM2kX0CxTFbyuvj0Qe4Onpvjyn+XbHNKPo XBAXv1fNIk1Mb3w== X-Received: by 2002:adf:fa02:: with SMTP id m2mr563555wrr.273.1600705806549; Mon, 21 Sep 2020 09:30:06 -0700 (PDT) X-Google-Smtp-Source: ABdhPJzuDGMPIjXlDaa/Q2cAnMtwWTcDs/LdCrlPAtloxT7TwCerzSsyfhCE1mhYxu9hvZLyV2rIhw== X-Received: by 2002:adf:fa02:: with SMTP id m2mr563529wrr.273.1600705806306; Mon, 21 Sep 2020 09:30:06 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Stefan Hajnoczi , qemu-devel@nongnu.org Cc: Kevin Wolf , Max Reitz , qemu-block@nongnu.org, Fam Zheng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/6] block/nvme: Reduce I/O registers scope Date: Mon, 21 Sep 2020 18:29:46 +0200 Message-Id: <20200921162949.553863-4-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200921162949.553863-1-philmd@redhat.com> References: <20200921162949.553863-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) We only access the I/O register in nvme_init(). Remove the reference in BDRVNVMeState and reduce its scope. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 29 ++++++++++++++++------------- 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index 3c834da8fec..e517c7539ff 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -98,7 +98,6 @@ enum { struct BDRVNVMeState { AioContext *aio_context; QEMUVFIOState *vfio; - NVMeRegs *regs; /* Memory mapped registers */ volatile struct { uint32_t sq_tail; @@ -695,6 +694,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, uint64_t timeout_ms; uint64_t deadline, now; Error *local_err =3D NULL; + NVMeRegs *regs; =20 qemu_co_mutex_init(&s->dma_map_lock); qemu_co_queue_init(&s->dma_flush_queue); @@ -713,16 +713,16 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, goto out; } =20 - s->regs =3D qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar), - PROT_READ | PROT_WRITE, errp); - if (!s->regs) { + regs =3D qemu_vfio_pci_map_bar(s->vfio, 0, 0, sizeof(NvmeBar), + PROT_READ | PROT_WRITE, errp); + if (!regs) { ret =3D -EINVAL; goto out; } /* Perform initialize sequence as described in NVMe spec "7.6.1 * Initialization". */ =20 - cap =3D le64_to_cpu(s->regs->ctrl.cap); + cap =3D le64_to_cpu(regs->ctrl.cap); if (!(cap & (1ULL << 37))) { error_setg(errp, "Device doesn't support NVMe command set"); ret =3D -EINVAL; @@ -735,10 +735,10 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, timeout_ms =3D MIN(500 * ((cap >> 24) & 0xFF), 30000); =20 /* Reset device to get a clean state. */ - s->regs->ctrl.cc =3D cpu_to_le32(le32_to_cpu(s->regs->ctrl.cc) & 0xFE); + regs->ctrl.cc =3D cpu_to_le32(le32_to_cpu(regs->ctrl.cc) & 0xFE); /* Wait for CSTS.RDY =3D 0. */ deadline =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCA= LE_MS; - while (le32_to_cpu(s->regs->ctrl.csts) & 0x1) { + while (le32_to_cpu(regs->ctrl.csts) & 0x1) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to reset (%" PRId64 " ms)", @@ -766,18 +766,18 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); - s->regs->ctrl.aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE= _SIZE); - s->regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); - s->regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); + regs->ctrl.aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SI= ZE); + regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); + regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); =20 /* After setting up all control registers we can enable device now. */ - s->regs->ctrl.cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | + regs->ctrl.cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 0x1); /* Wait for CSTS.RDY =3D 1. */ now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); deadline =3D now + timeout_ms * 1000000; - while (!(le32_to_cpu(s->regs->ctrl.csts) & 0x1)) { + while (!(le32_to_cpu(regs->ctrl.csts) & 0x1)) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to start (%" PRId64 " ms)", @@ -808,6 +808,10 @@ static int nvme_init(BlockDriverState *bs, const char = *device, int namespace, ret =3D -EIO; } out: + if (regs) { + qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)regs, 0, sizeof(NvmeBa= r)); + } + /* Cleaning up is done in nvme_file_open() upon error. */ return ret; } @@ -882,7 +886,6 @@ static void nvme_close(BlockDriverState *bs) event_notifier_cleanup(&s->irq_notifier[MSIX_SHARED_IRQ_IDX]); qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->doorbells, sizeof(NvmeBar), NVME_DOORBELL_SIZE); - qemu_vfio_pci_unmap_bar(s->vfio, 0, (void *)s->regs, 0, sizeof(NvmeBar= )); qemu_vfio_close(s->vfio); =20 g_free(s->device); --=20 2.26.2