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[83.57.170.65]) by smtp.gmail.com with ESMTPSA id a17sm19633754wra.24.2020.09.20.20.52.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2020 20:53:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dcCXq9EmDF/ND5OQIcbMSYGFUbh9qfqOjQv8VK2LW0A=; b=ZXz6++ulUuofMXLwMdkIFvVYbVfptOwYGMHDECsZA2fVY/cXk4fKyoqg8+K8RGdTVV WMFFpIPcfH3iP4DO1Gzeo3RY1gpQrkwrzpUc27+vRG03RExbSU/QWPUpwpu5N+pnYky5 dchThiTyq1ovWX4xeYh6Qz0Sc30T09qD49SAUacGFsqaMHY7HBrMMc1UpPUGoA1Nq7Mt d8FhUvZcyF3qojmnUC6gTXJypfbIi1m2iuWi5p5AEKIp6lAan2FV0G3668A3Tkrr+0ZK jPvp0qaYollresdg8LSy2rxK5IGt/3Rn66drq2WT5eXUre5vkSj7zS8qtSzGwEPFI9i1 galg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dcCXq9EmDF/ND5OQIcbMSYGFUbh9qfqOjQv8VK2LW0A=; b=m1H5BFBts352GImewM4Vf2Wi/wxJ0blVSiweRHOrBTxZLkM/+FtON4wVnkxTOJGFob 3akFjRPWKzcjCbd+rM8Jr1AkIHL08RzF6yuyHqCLdeWmcN7tFGYgmvVAdkpAHR34ide3 CUh9yFcNl9fsXkK084pSSEqD0YMCqRWa0UBK3PqxfGZ5LCydhBP4a2PMGqSbGdvvJD2P iw02JPRs4JM4ZP5dAVXUg1/+Accx3B9f0n0LPqdwuLNBGZfkIneU3id7g6Ic0cl1+CZU CsvNhiQ7gUH88PH/rOdE5s1wtGk7QbZjoXpiK5w95+bsliqYq+NtBh/8xOQF/inubjP/ 34Aw== X-Gm-Message-State: AOAM533r6adJbkdKIyx3z+02rIUkhhMRmGb5I2PjyAUUcsmboZswvfC2 oNohHVG7uxjvVyylIxB10o4= X-Google-Smtp-Source: ABdhPJwRl3Z5WIikTR6gR38co3WDSTZo81ph0bORf7hpIY/ds2mvi4K2+q+lEmrWAxcDsY8qPqIWYA== X-Received: by 2002:a1c:7e15:: with SMTP id z21mr27599378wmc.21.1600660381007; Sun, 20 Sep 2020 20:53:01 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrew Baumann , Luc Michel , qemu-arm@nongnu.org, Peter Maydell , Niek Linnenbank , Paul Zimmerman , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/5] hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers Date: Mon, 21 Sep 2020 05:52:53 +0200 Message-Id: <20200921035257.434532-2-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200921035257.434532-1-f4bug@amsat.org> References: <20200921035257.434532-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) Add trace events for GPU and CPU IRQs. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Luc Michel --- hw/intc/bcm2835_ic.c | 4 +++- hw/intc/trace-events | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/bcm2835_ic.c b/hw/intc/bcm2835_ic.c index 53ab8f58810..9000d995e81 100644 --- a/hw/intc/bcm2835_ic.c +++ b/hw/intc/bcm2835_ic.c @@ -18,6 +18,7 @@ #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "trace.h" =20 #define GPU_IRQS 64 #define ARM_IRQS 8 @@ -51,7 +52,6 @@ static void bcm2835_ic_update(BCM2835ICState *s) set =3D (s->gpu_irq_level & s->gpu_irq_enable) || (s->arm_irq_level & s->arm_irq_enable); qemu_set_irq(s->irq, set); - } =20 static void bcm2835_ic_set_gpu_irq(void *opaque, int irq, int level) @@ -59,6 +59,7 @@ static void bcm2835_ic_set_gpu_irq(void *opaque, int irq,= int level) BCM2835ICState *s =3D opaque; =20 assert(irq >=3D 0 && irq < 64); + trace_bcm2835_ic_set_gpu_irq(irq, level); s->gpu_irq_level =3D deposit64(s->gpu_irq_level, irq, 1, level !=3D 0); bcm2835_ic_update(s); } @@ -68,6 +69,7 @@ static void bcm2835_ic_set_arm_irq(void *opaque, int irq,= int level) BCM2835ICState *s =3D opaque; =20 assert(irq >=3D 0 && irq < 8); + trace_bcm2835_ic_set_cpu_irq(irq, level); s->arm_irq_level =3D deposit32(s->arm_irq_level, irq, 1, level !=3D 0); bcm2835_ic_update(s); } diff --git a/hw/intc/trace-events b/hw/intc/trace-events index 527c3f76cae..22782b3f089 100644 --- a/hw/intc/trace-events +++ b/hw/intc/trace-events @@ -199,3 +199,7 @@ nvic_sysreg_write(uint64_t addr, uint32_t value, unsign= ed size) "NVIC sysreg wri heathrow_write(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64"= %u: 0x%"PRIx64 heathrow_read(uint64_t addr, unsigned int n, uint64_t value) "0x%"PRIx64" = %u: 0x%"PRIx64 heathrow_set_irq(int num, int level) "set_irq: num=3D0x%02x level=3D%d" + +# bcm2835_ic.c +bcm2835_ic_set_gpu_irq(int irq, int level) "GPU irq #%d level %d" +bcm2835_ic_set_cpu_irq(int irq, int level) "CPU irq #%d level %d" --=20 2.26.2