From nobody Mon Feb 9 22:20:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.66 as permitted sender) client-ip=209.85.128.66; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f66.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1600624717; cv=none; d=zohomail.com; s=zohoarc; b=c2sW1tZcRCCvAPXrisl3hM3oGvWaw+wb0Ls3C2vYanvrtnMB7XjrqmsIpQ/wFO0+Zlz4Qpb+2n2S7FayV8GAYIm2WBKZDIbk2r6jQpbYZd0b5vxdS/27cKCgh0XLzrX4NkDfEEtYYASplZIXxuVcNM2WNhWhQrH1tQcgI7jjwS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600624717; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZsGklvGCCEfAG2C9pvK94uYRWIB54oFE2Bd5BK/jcb8=; b=Sz5004vtprj6lUaNCdbzMMvUt854HclpZbOJOOpjHYq3h2e7f/X78IGnU+wC3iPU6Vnj+9XqeVEKbsimJ05nh2cJ3TQBtGdHLBKBcWc+9QqSZd3DROHmfB7hGNOsGrMmZBD8CbNf+4tJYURJlDoeNssCq7phapr8P3rfZfVwonk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.66 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=fail header.from= (p=none dis=none) header.from= Received: from mail-wm1-f66.google.com (mail-wm1-f66.google.com [209.85.128.66]) by mx.zohomail.com with SMTPS id 1600624717490420.9841431047955; Sun, 20 Sep 2020 10:58:37 -0700 (PDT) Received: by mail-wm1-f66.google.com with SMTP id e17so9957136wme.0 for ; Sun, 20 Sep 2020 10:58:36 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (65.red-83-57-170.dynamicip.rima-tde.net. [83.57.170.65]) by smtp.gmail.com with ESMTPSA id u66sm15675781wme.12.2020.09.20.10.58.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2020 10:58:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZsGklvGCCEfAG2C9pvK94uYRWIB54oFE2Bd5BK/jcb8=; b=TkB3zzCeI8YhT2U6WxycJrsinLA87pX1heBznbc6QoAumbTiblsnhocnhiFikIH3v5 DK6JmphQDVPGRuaO40U3eERiPmElnP2CmbwInxA4QbCGsawVQ8IYkf3AcTq+btdh/Xc6 BZDZH4ITChGmXL8o8cwbpJW8VWZWHM2mWNqYtjggk2IVBU0FoUGf/DZRpb1bpkkHxbps 3YnKVP+WbyWQ0W7uBKEUzPyb0I8lyTP4gj8wf0nFpOQTV18Tn8MB9N2ZvcYL9U1PIYay 0bTTBiK1YS0OUMTGQiFdYfKUBMb7Go1ObIvLlWTJiOg6eK5m73Qp+rdEsBCJOeF71kK0 fysw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=ZsGklvGCCEfAG2C9pvK94uYRWIB54oFE2Bd5BK/jcb8=; b=Y3FtZ5Q2kIfyGRuBYanN+1sNmgW0+/K4FxMQncF5WlNEQ8scxMPCNfDVXTr0n7bk/O TOwNWJhEJlPqAVkSxR/7olFCRSk5R4txGNxs95dCXeVkhlJuwPdRQlhgFVUMHEBOJ0Z4 OnXG/Cw1OUbrEVZrafo6t524Z6Zjm4OkR20eTkNbsDzkK1nlEif+UtC7XvS5w6SQMRyI K6dgxUHxTTFrrOljfqW9+5K8dyHzqcst5T8195BpfFgCq3nSWXgNmPv66Pa+ChwnKZ4U 165K02WWIfXMtofUZQk4BY32gI3BSj940wgesLTE7e0DxwApQ6KfAlL3LUM5kkNMtMGS W0+g== X-Gm-Message-State: AOAM532WMO4Mx+XOJPhlsHCHKr/PN7C0evo1Ran4DTWxCQ/ZuN1F+1x4 HffJ+FAIPBAaY6n0KiGIx1NhV0ruLB8= X-Google-Smtp-Source: ABdhPJy6Vc3n8ekSzzB73iq7sVKYYDnQmUtwP3i5TmEvgsjaoQE29zscia6PUjuhmdI5hMQf5wdrxg== X-Received: by 2002:a1c:7f8b:: with SMTP id a133mr27881664wmd.155.1600624715498; Sun, 20 Sep 2020 10:58:35 -0700 (PDT) Sender: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Niek Linnenbank , Peter Maydell , Paul Zimmerman , Andrew Baumann , Luc Michel Subject: [PATCH 6/7] hw/timer/bcm2835: Support the timer COMPARE registers Date: Sun, 20 Sep 2020 19:58:24 +0200 Message-Id: <20200920175825.417680-7-f4bug@amsat.org> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200920175825.417680-1-f4bug@amsat.org> References: <20200920175825.417680-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) This peripheral has 1 free-running timer and 4 compare registers. Only the free-running timer is implemented. Add support the COMPARE registers (each register is wired to an IRQ). Reference: "BCM2835 ARM Peripherals" datasheet [*] chapter 12 "System Timer": The System Timer peripheral provides four 32-bit timer channels and a single 64-bit free running counter. Each channel has an output compare register, which is compared against the 32 least significant bits of the free running counter values. When the two values match, the system timer peripheral generates a signal to indicate a match for the appropriate channel. The match signal is then fed into the interrupt controller. This peripheral is used since Linux 3.7, commit ee4af5696720 ("ARM: bcm2835: add system timer"). [*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals= .pdf Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/timer/bcm2835_systmr.h | 11 +++++++-- hw/timer/bcm2835_systmr.c | 41 +++++++++++++++++++------------ hw/timer/trace-events | 4 ++- 3 files changed, 37 insertions(+), 19 deletions(-) diff --git a/include/hw/timer/bcm2835_systmr.h b/include/hw/timer/bcm2835_s= ystmr.h index e0db9e9e12b..17fdd9d67b2 100644 --- a/include/hw/timer/bcm2835_systmr.h +++ b/include/hw/timer/bcm2835_systmr.h @@ -11,6 +11,7 @@ =20 #include "hw/sysbus.h" #include "hw/irq.h" +#include "qemu/timer.h" #include "qom/object.h" =20 #define TYPE_BCM2835_SYSTIMER "bcm2835-sys-timer" @@ -20,18 +21,24 @@ DECLARE_INSTANCE_CHECKER(BCM2835SystemTimerState, BCM28= 35_SYSTIMER, =20 #define BCM2835_SYSTIMER_COUNT 4 =20 +typedef struct { + unsigned id; + QEMUTimer timer; + qemu_irq irq; + BCM2835SystemTimerState *state; +} BCM2835SystemTimerCompare; + struct BCM2835SystemTimerState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion iomem; - qemu_irq irq; - struct { uint32_t ctrl_status; uint32_t compare[BCM2835_SYSTIMER_COUNT]; } reg; + BCM2835SystemTimerCompare tmr[BCM2835_SYSTIMER_COUNT]; }; =20 #endif diff --git a/hw/timer/bcm2835_systmr.c b/hw/timer/bcm2835_systmr.c index b234e83824f..43e644f5e45 100644 --- a/hw/timer/bcm2835_systmr.c +++ b/hw/timer/bcm2835_systmr.c @@ -28,20 +28,13 @@ REG32(COMPARE1, 0x10) REG32(COMPARE2, 0x14) REG32(COMPARE3, 0x18) =20 -static void bcm2835_systmr_update_irq(BCM2835SystemTimerState *s) +static void bcm2835_systmr_timer_expire(void *opaque) { - bool enable =3D !!s->reg.ctrl_status; + BCM2835SystemTimerCompare *tmr =3D opaque; =20 - trace_bcm2835_systmr_irq(enable); - qemu_set_irq(s->irq, enable); -} - -static void bcm2835_systmr_update_compare(BCM2835SystemTimerState *s, - unsigned timer_index) -{ - /* TODO fow now, since neither Linux nor U-boot use these timers. */ - qemu_log_mask(LOG_UNIMP, "COMPARE register %u not implemented\n", - timer_index); + trace_bcm2835_systmr_timer_expired(tmr->id); + tmr->state->reg.ctrl_status |=3D 1 << tmr->id; + qemu_set_irq(tmr->irq, 1); } =20 static uint64_t bcm2835_systmr_read(void *opaque, hwaddr offset, @@ -78,16 +71,25 @@ static void bcm2835_systmr_write(void *opaque, hwaddr o= ffset, uint64_t value, unsigned size) { BCM2835SystemTimerState *s =3D BCM2835_SYSTIMER(opaque); + int index; =20 trace_bcm2835_systmr_write(offset, value); switch (offset) { case A_CTRL_STATUS: s->reg.ctrl_status &=3D ~value; /* Ack */ - bcm2835_systmr_update_irq(s); + for (index =3D 0; index < ARRAY_SIZE(s->tmr); index++) { + if (extract32(value, index, 1)) { + trace_bcm2835_systmr_irq_ack(index); + qemu_set_irq(s->tmr[index].irq, 0); + } + } break; case A_COMPARE0 ... A_COMPARE3: - s->reg.compare[(offset - A_COMPARE0) >> 2] =3D value; - bcm2835_systmr_update_compare(s, (offset - A_COMPARE0) >> 2); + index =3D (offset - A_COMPARE0) >> 2; + s->reg.compare[index] =3D value; + timer_mod(&s->tmr[index].timer, value); + trace_bcm2835_systmr_run(index, + value - qemu_clock_get_us(QEMU_CLOCK_VIRT= UAL)); break; case A_COUNTER_LOW: case A_COUNTER_HIGH: @@ -125,7 +127,14 @@ static void bcm2835_systmr_realize(DeviceState *dev, E= rror **errp) memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_systmr_ops, s, "bcm2835-sys-timer", 0x20); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); - sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + for (size_t i =3D 0; i < ARRAY_SIZE(s->tmr); i++) { + s->tmr[i].id =3D i; + s->tmr[i].state =3D s; + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->tmr[i].irq); + timer_init_us(&s->tmr[i].timer, QEMU_CLOCK_VIRTUAL, + bcm2835_systmr_timer_expire, &s->tmr[i]); + } } =20 static const VMStateDescription bcm2835_systmr_vmstate =3D { diff --git a/hw/timer/trace-events b/hw/timer/trace-events index b996d992000..f4ca31d4951 100644 --- a/hw/timer/trace-events +++ b/hw/timer/trace-events @@ -77,9 +77,11 @@ nrf51_timer_write(uint8_t timer_id, uint64_t addr, uint3= 2_t value, unsigned size nrf51_timer_set_count(uint8_t timer_id, uint8_t counter_id, uint32_t value= ) "timer %u counter %u count 0x%" PRIx32 =20 # bcm2835_systmr.c -bcm2835_systmr_irq(bool enable) "timer irq state %u" +bcm2835_systmr_timer_expired(unsigned id) "timer #%u expired" +bcm2835_systmr_irq_ack(unsigned id) "timer #%u acked" bcm2835_systmr_read(uint64_t offset, uint64_t data) "timer read: offset 0x= %" PRIx64 " data 0x%" PRIx64 bcm2835_systmr_write(uint64_t offset, uint64_t data) "timer write: offset = 0x%" PRIx64 " data 0x%" PRIx64 +bcm2835_systmr_run(unsigned id, uint64_t delay_us) "timer #%u expiring in = %"PRIu64" us" =20 # avr_timer16.c avr_timer16_read(uint8_t addr, uint8_t value) "timer16 read addr:%u value:= %u" --=20 2.26.2