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bh=u4VsQlbRFe7gSlcn7swxt6vr6RZN1WLwF/0IcfEatK8=; b=NVYOtulyjMzxtTnaxzt685U0b1CJeAMflmYFI/VZ2JWPbHmCsvscoy8H+Yy/wTG4gKRdrT pejNN04sH8dstOv4mETDbUC03TZHdO5ewffC5WpVrYs4ls28wIYhieusVBXoMxqIIgX5cW vmQAr5Ul3LcPi1vQBhH8D8rc2AGm1H4= X-MC-Unique: 3X40T3VbNVmxBYTO-7Ufng-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 03/17] sifive: Move QOM typedefs and add missing includes Date: Fri, 18 Sep 2020 16:47:00 -0400 Message-Id: <20200918204714.27276-4-ehabkost@redhat.com> In-Reply-To: <20200918204714.27276-1-ehabkost@redhat.com> References: <20200918204714.27276-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.139.110.61; envelope-from=ehabkost@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/18 16:47:22 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -50 X-Spam_score: -5.1 X-Spam_bar: ----- X-Spam_report: (-5.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-2.999, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) Some typedefs and macros are defined after the type check macros. This makes it difficult to automatically replace their definitions with OBJECT_DECLARE_TYPE. Patch generated using: $ ./scripts/codeconverter/converter.py -i \ --pattern=3DQOMStructTypedefSplit $(git grep -l '' -- '*.[ch]') which will split "typdef struct { ... } TypedefName" declarations. Followed by: $ ./scripts/codeconverter/converter.py -i --pattern=3DMoveSymbols \ $(git grep -l '' -- '*.[ch]') which will: - move the typedefs and #defines above the type check macros - add missing #include "qom/object.h" lines if necessary Signed-off-by: Eduardo Habkost Reviewed-by: Daniel P. Berrang=C3=A9 Message-Id: <20200831210740.126168-9-ehabkost@redhat.com> Signed-off-by: Eduardo Habkost --- hw/intc/sifive_plic.h | 6 ++++-- include/hw/char/sifive_uart.h | 6 ++++-- include/hw/gpio/sifive_gpio.h | 6 ++++-- include/hw/misc/sifive_e_prci.h | 6 ++++-- include/hw/misc/sifive_test.h | 6 ++++-- include/hw/misc/sifive_u_otp.h | 6 ++++-- include/hw/misc/sifive_u_prci.h | 6 ++++-- 7 files changed, 28 insertions(+), 14 deletions(-) diff --git a/hw/intc/sifive_plic.h b/hw/intc/sifive_plic.h index ace76d0f1b..aa6ae13c3a 100644 --- a/hw/intc/sifive_plic.h +++ b/hw/intc/sifive_plic.h @@ -22,9 +22,11 @@ #define HW_SIFIVE_PLIC_H =20 #include "hw/sysbus.h" +#include "qom/object.h" =20 #define TYPE_SIFIVE_PLIC "riscv.sifive.plic" =20 +typedef struct SiFivePLICState SiFivePLICState; #define SIFIVE_PLIC(obj) \ OBJECT_CHECK(SiFivePLICState, (obj), TYPE_SIFIVE_PLIC) =20 @@ -41,7 +43,7 @@ typedef struct PLICAddr { PLICMode mode; } PLICAddr; =20 -typedef struct SiFivePLICState { +struct SiFivePLICState { /*< private >*/ SysBusDevice parent_obj; =20 @@ -69,7 +71,7 @@ typedef struct SiFivePLICState { uint32_t context_base; uint32_t context_stride; uint32_t aperture_size; -} SiFivePLICState; +}; =20 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t hartid_base, uint32_t num_sources, diff --git a/include/hw/char/sifive_uart.h b/include/hw/char/sifive_uart.h index 65668825a3..2bb72ac80b 100644 --- a/include/hw/char/sifive_uart.h +++ b/include/hw/char/sifive_uart.h @@ -22,6 +22,7 @@ =20 #include "chardev/char-fe.h" #include "hw/sysbus.h" +#include "qom/object.h" =20 enum { SIFIVE_UART_TXFIFO =3D 0, @@ -51,10 +52,11 @@ enum { =20 #define TYPE_SIFIVE_UART "riscv.sifive.uart" =20 +typedef struct SiFiveUARTState SiFiveUARTState; #define SIFIVE_UART(obj) \ OBJECT_CHECK(SiFiveUARTState, (obj), TYPE_SIFIVE_UART) =20 -typedef struct SiFiveUARTState { +struct SiFiveUARTState { /*< private >*/ SysBusDevice parent_obj; =20 @@ -69,7 +71,7 @@ typedef struct SiFiveUARTState { uint32_t txctrl; uint32_t rxctrl; uint32_t div; -} SiFiveUARTState; +}; =20 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr ba= se, Chardev *chr, qemu_irq irq); diff --git a/include/hw/gpio/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h index cf12fcfd62..af991fa44e 100644 --- a/include/hw/gpio/sifive_gpio.h +++ b/include/hw/gpio/sifive_gpio.h @@ -15,8 +15,10 @@ #define SIFIVE_GPIO_H =20 #include "hw/sysbus.h" +#include "qom/object.h" =20 #define TYPE_SIFIVE_GPIO "sifive_soc.gpio" +typedef struct SIFIVEGPIOState SIFIVEGPIOState; #define SIFIVE_GPIO(obj) OBJECT_CHECK(SIFIVEGPIOState, (obj), TYPE_SIFIVE_= GPIO) =20 #define SIFIVE_GPIO_PINS 32 @@ -41,7 +43,7 @@ #define SIFIVE_GPIO_REG_IOF_SEL 0x03C #define SIFIVE_GPIO_REG_OUT_XOR 0x040 =20 -typedef struct SIFIVEGPIOState { +struct SIFIVEGPIOState { SysBusDevice parent_obj; =20 MemoryRegion mmio; @@ -71,6 +73,6 @@ typedef struct SIFIVEGPIOState { =20 /* config */ uint32_t ngpio; -} SIFIVEGPIOState; +}; =20 #endif /* SIFIVE_GPIO_H */ diff --git a/include/hw/misc/sifive_e_prci.h b/include/hw/misc/sifive_e_prc= i.h index 698b0b451c..de1e502eea 100644 --- a/include/hw/misc/sifive_e_prci.h +++ b/include/hw/misc/sifive_e_prci.h @@ -18,6 +18,7 @@ =20 #ifndef HW_SIFIVE_E_PRCI_H #define HW_SIFIVE_E_PRCI_H +#include "qom/object.h" =20 enum { SIFIVE_E_PRCI_HFROSCCFG =3D 0x0, @@ -51,10 +52,11 @@ enum { =20 #define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" =20 +typedef struct SiFiveEPRCIState SiFiveEPRCIState; #define SIFIVE_E_PRCI(obj) \ OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI) =20 -typedef struct SiFiveEPRCIState { +struct SiFiveEPRCIState { /*< private >*/ SysBusDevice parent_obj; =20 @@ -64,7 +66,7 @@ typedef struct SiFiveEPRCIState { uint32_t hfxosccfg; uint32_t pllcfg; uint32_t plloutdiv; -} SiFiveEPRCIState; +}; =20 DeviceState *sifive_e_prci_create(hwaddr addr); =20 diff --git a/include/hw/misc/sifive_test.h b/include/hw/misc/sifive_test.h index 1ec416ac1b..dc54b7af0c 100644 --- a/include/hw/misc/sifive_test.h +++ b/include/hw/misc/sifive_test.h @@ -20,19 +20,21 @@ #define HW_SIFIVE_TEST_H =20 #include "hw/sysbus.h" +#include "qom/object.h" =20 #define TYPE_SIFIVE_TEST "riscv.sifive.test" =20 +typedef struct SiFiveTestState SiFiveTestState; #define SIFIVE_TEST(obj) \ OBJECT_CHECK(SiFiveTestState, (obj), TYPE_SIFIVE_TEST) =20 -typedef struct SiFiveTestState { +struct SiFiveTestState { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ MemoryRegion mmio; -} SiFiveTestState; +}; =20 enum { FINISHER_FAIL =3D 0x3333, diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h index 639297564a..4572534f50 100644 --- a/include/hw/misc/sifive_u_otp.h +++ b/include/hw/misc/sifive_u_otp.h @@ -18,6 +18,7 @@ =20 #ifndef HW_SIFIVE_U_OTP_H #define HW_SIFIVE_U_OTP_H +#include "qom/object.h" =20 #define SIFIVE_U_OTP_PA 0x00 #define SIFIVE_U_OTP_PAIO 0x04 @@ -49,10 +50,11 @@ =20 #define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" =20 +typedef struct SiFiveUOTPState SiFiveUOTPState; #define SIFIVE_U_OTP(obj) \ OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) =20 -typedef struct SiFiveUOTPState { +struct SiFiveUOTPState { /*< private >*/ SysBusDevice parent_obj; =20 @@ -75,6 +77,6 @@ typedef struct SiFiveUOTPState { uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; /* config */ uint32_t serial; -} SiFiveUOTPState; +}; =20 #endif /* HW_SIFIVE_U_OTP_H */ diff --git a/include/hw/misc/sifive_u_prci.h b/include/hw/misc/sifive_u_prc= i.h index 0a531fdadc..83eab43686 100644 --- a/include/hw/misc/sifive_u_prci.h +++ b/include/hw/misc/sifive_u_prci.h @@ -18,6 +18,7 @@ =20 #ifndef HW_SIFIVE_U_PRCI_H #define HW_SIFIVE_U_PRCI_H +#include "qom/object.h" =20 #define SIFIVE_U_PRCI_HFXOSCCFG 0x00 #define SIFIVE_U_PRCI_COREPLLCFG0 0x04 @@ -58,10 +59,11 @@ =20 #define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" =20 +typedef struct SiFiveUPRCIState SiFiveUPRCIState; #define SIFIVE_U_PRCI(obj) \ OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI) =20 -typedef struct SiFiveUPRCIState { +struct SiFiveUPRCIState { /*< private >*/ SysBusDevice parent_obj; =20 @@ -76,7 +78,7 @@ typedef struct SiFiveUPRCIState { uint32_t coreclksel; uint32_t devicesreset; uint32_t clkmuxstatus; -} SiFiveUPRCIState; +}; =20 /* * Clock indexes for use by Device Tree data and the PRCI driver. --=20 2.26.2