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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::442; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x442.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 10 ++++ target/arm/sve.decode | 9 ++++ target/arm/sve_helper.c | 99 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sve.c | 17 +++++++ 4 files changed, 135 insertions(+) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 9542f01c42..4af5e1a5ce 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -2784,3 +2784,13 @@ DEF_HELPER_FLAGS_5(sve2_fcvtlt_sd, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(flogb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(flogb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(flogb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve2_cdot_zzzz_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_cdot_zzzz_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve2_cdot_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_cdot_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sve.decode b/target/arm/sve.decode index 6708c048e0..84232ff9e5 100644 --- a/target/arm/sve.decode +++ b/target/arm/sve.decode @@ -811,6 +811,9 @@ MUL_zzi 00100101 .. 110 000 110 ........ ..... = @rdn_i8s DOT_zzzz 01000100 1 sz:1 0 rm:5 00000 u:1 rn:5 rd:5 \ ra=3D%reg_movprfx =20 +# SVE2 complex dot product (vectors) +CDOT_zzzz 01000100 esz:2 0 rm:5 0001 rot:2 rn:5 rd:5 ra=3D%reg_movp= rfx + #### SVE Multiply - Indexed =20 # SVE integer dot product (indexed) @@ -849,6 +852,12 @@ SQDMLSLB_zzxw_d 01000100 .. 1 ..... 0011.0 ..... .....= @rrxw_d SQDMLSLT_zzxw_s 01000100 .. 1 ..... 0011.1 ..... ..... @rrxw_s SQDMLSLT_zzxw_d 01000100 .. 1 ..... 0011.1 ..... ..... @rrxw_d =20 +# SVE2 complex integer dot product (indexed) +CDOT_zzxw_s 01000100 10 1 index:2 rm:3 0100 rot:2 rn:5 rd:5 \ + ra=3D%reg_movprfx +CDOT_zzxw_d 01000100 11 1 index:1 rm:4 0100 rot:2 rn:5 rd:5 \ + ra=3D%reg_movprfx + # SVE2 complex integer multiply-add (indexed) CMLA_zzxz_h 01000100 10 1 index:2 rm:3 0110 rot:2 rn:5 rd:5 \ ra=3D%reg_movprfx diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index ef04a0f95a..0ff5e0baf8 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -1592,6 +1592,105 @@ void HELPER(sve2_sqrdcmlah_idx_s)(void *vd, void *v= n, void *vm, do_cmla_idx_s(vd, vn, vm, va, desc, do_sqrdcmlah_s); } =20 +/* Note N and M are 4 elements bundled into one unit. */ +static int32_t do_cdot_s(uint32_t n, uint32_t m, int32_t a, + int sel_a, int sel_b, int sub_i) +{ + for (int i =3D 0; i <=3D 1; i++) { + int32_t elt1_r =3D (int8_t)(n >> (16 * i)); + int32_t elt1_i =3D (int8_t)(n >> (16 * i + 8)); + int32_t elt2_a =3D (int8_t)(m >> (16 * i + 8 * sel_a)); + int32_t elt2_b =3D (int8_t)(m >> (16 * i + 8 * sel_b)); + + a +=3D elt1_r * elt2_a + elt1_i * elt2_b * sub_i; + } + return a; +} + +static int64_t do_cdot_d(uint64_t n, uint64_t m, int64_t a, + int sel_a, int sel_b, int sub_i) +{ + for (int i =3D 0; i <=3D 1; i++) { + int64_t elt1_r =3D (int16_t)(n >> (32 * i + 0)); + int64_t elt1_i =3D (int16_t)(n >> (32 * i + 16)); + int64_t elt2_a =3D (int16_t)(m >> (32 * i + 16 * sel_a)); + int64_t elt2_b =3D (int16_t)(m >> (32 * i + 16 * sel_b)); + + a +=3D elt1_r * elt2_a + elt1_i * elt2_b * sub_i; + } + return a; +} + +void HELPER(sve2_cdot_zzzz_s)(void *vd, void *vn, void *vm, + void *va, uint32_t desc) +{ + int opr_sz =3D simd_oprsz(desc); + int rot =3D simd_data(desc); + int sel_a =3D rot & 1; + int sel_b =3D sel_a ^ 1; + int sub_i =3D (rot =3D=3D 0 || rot =3D=3D 3 ? -1 : 1); + uint32_t *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; + + for (int e =3D 0; e < opr_sz / 4; e++) { + d[e] =3D do_cdot_s(n[e], m[e], a[e], sel_a, sel_b, sub_i); + } +} + +void HELPER(sve2_cdot_zzzz_d)(void *vd, void *vn, void *vm, + void *va, uint32_t desc) +{ + int opr_sz =3D simd_oprsz(desc); + int rot =3D simd_data(desc); + int sel_a =3D rot & 1; + int sel_b =3D sel_a ^ 1; + int sub_i =3D (rot =3D=3D 0 || rot =3D=3D 3 ? -1 : 1); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; + + for (int e =3D 0; e < opr_sz / 8; e++) { + d[e] =3D do_cdot_d(n[e], m[e], a[e], sel_a, sel_b, sub_i); + } +} + +void HELPER(sve2_cdot_idx_s)(void *vd, void *vn, void *vm, + void *va, uint32_t desc) +{ + int opr_sz =3D simd_oprsz(desc); + int rot =3D extract32(desc, SIMD_DATA_SHIFT, 2); + int idx =3D H4(extract32(desc, SIMD_DATA_SHIFT + 2, 2)); + int sel_a =3D rot & 1; + int sel_b =3D sel_a ^ 1; + int sub_i =3D (rot =3D=3D 0 || rot =3D=3D 3 ? -1 : 1); + uint32_t *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; + + for (int seg =3D 0; seg < opr_sz / 4; seg +=3D 4) { + uint32_t seg_m =3D m[seg + idx]; + for (int e =3D 0; e < 4; e++) { + d[seg + e] =3D do_cdot_s(n[seg + e], seg_m, a[seg + e], + sel_a, sel_b, sub_i); + } + } +} + +void HELPER(sve2_cdot_idx_d)(void *vd, void *vn, void *vm, + void *va, uint32_t desc) +{ + int seg, opr_sz =3D simd_oprsz(desc); + int rot =3D extract32(desc, SIMD_DATA_SHIFT, 2); + int idx =3D extract32(desc, SIMD_DATA_SHIFT + 2, 2); + int sel_a =3D rot & 1; + int sel_b =3D sel_a ^ 1; + int sub_i =3D (rot =3D=3D 0 || rot =3D=3D 3 ? -1 : 1); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm, *a =3D va; + + for (seg =3D 0; seg < opr_sz / 8; seg +=3D 2) { + uint64_t seg_m =3D m[seg + idx]; + for (int e =3D 0; e < 2; e++) { + d[seg + e] =3D do_cdot_d(n[seg + e], seg_m, a[seg + e], + sel_a, sel_b, sub_i); + } + } +} + #define DO_ZZXZ(NAME, TYPE, H, OP) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *va, uint32_t desc) \ { \ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 92d1297a5c..4893968cdb 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4151,6 +4151,9 @@ DO_SVE2_RRXR_ROT(CMLA_zzxz_s, gen_helper_sve2_cmla_id= x_s) DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_h, gen_helper_sve2_sqrdcmlah_idx_h) DO_SVE2_RRXR_ROT(SQRDCMLAH_zzxz_s, gen_helper_sve2_sqrdcmlah_idx_s) =20 +DO_SVE2_RRXR_ROT(CDOT_zzxw_s, gen_helper_sve2_cdot_idx_s) +DO_SVE2_RRXR_ROT(CDOT_zzxw_d, gen_helper_sve2_cdot_idx_d) + #undef DO_SVE2_RRXR_ROT =20 /* @@ -8355,6 +8358,20 @@ static bool trans_CMLA_zzzz(DisasContext *s, arg_CML= A_zzzz *a) return true; } =20 +static bool trans_CDOT_zzzz(DisasContext *s, arg_CMLA_zzzz *a) +{ + if (!dc_isar_feature(aa64_sve2, s) || a->esz < MO_32) { + return false; + } + if (sve_access_check(s)) { + gen_helper_gvec_4 *fn =3D (a->esz =3D=3D MO_32 + ? gen_helper_sve2_cdot_zzzz_s + : gen_helper_sve2_cdot_zzzz_d); + gen_gvec_ool_zzzz(s, fn, a->rd, a->rn, a->rm, a->ra, a->rot); + } + return true; +} + static bool trans_SQRDCMLAH_zzzz(DisasContext *s, arg_SQRDCMLAH_zzzz *a) { static gen_helper_gvec_4 * const fns[] =3D { --=20 2.25.1