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charset="utf-8" Support devicetree CPU cache information descriptions Signed-off-by: Ying Fang --- hw/arm/virt.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 71f7dbb317..74b748ae35 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -343,6 +343,89 @@ static void fdt_add_timer_nodes(const VirtMachineState= *vms) GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqfla= gs); } =20 +static void fdt_add_l3cache_nodes(const VirtMachineState *vms) +{ + int i; + const MachineState *ms =3D MACHINE(vms); + ARMCPU *cpu =3D ARM_CPU(first_cpu); + unsigned int smp_cores =3D ms->smp.cores; + unsigned int sockets =3D ms->smp.max_cpus / smp_cores; + + for (i =3D 0; i < sockets; i++) { + char *nodename =3D g_strdup_printf("/cpus/l3-cache%d", i); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cache"); + qemu_fdt_setprop_string(vms->fdt, nodename, "cache-unified", "true= "); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-level", 3); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-size", + cpu->caches.l3_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-line-size", + cpu->caches.l3_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-sets", + cpu->caches.l3_cache->sets); + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(vms->fdt)); + g_free(nodename); + } +} + +static void fdt_add_l2cache_nodes(const VirtMachineState *vms) +{ + int i, j; + const MachineState *ms =3D MACHINE(vms); + unsigned int smp_cores =3D ms->smp.cores; + signed int sockets =3D ms->smp.max_cpus / smp_cores; + ARMCPU *cpu =3D ARM_CPU(first_cpu); + + for (i =3D 0; i < sockets; i++) { + char *next_path =3D g_strdup_printf("/cpus/l3-cache%d", i); + for (j =3D 0; j < smp_cores; j++) { + char *nodename =3D g_strdup_printf("/cpus/l2-cache%d", + i * smp_cores + j); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cac= he"); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-size", + cpu->caches.l2_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-line-size", + cpu->caches.l2_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-sets", + cpu->caches.l2_cache->sets); + qemu_fdt_setprop_phandle(vms->fdt, nodename, + "next-level-cache", next_path); + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(vms->fdt)); + g_free(nodename); + } + g_free(next_path); + } +} + +static void fdt_add_l1cache_prop(const VirtMachineState *vms, + char *nodename, int cpu_index) +{ + + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(cpu_index)); + CPUCaches caches =3D cpu->caches; + + char *cachename =3D g_strdup_printf("/cpus/l2-cache%d", cpu_index); + + qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-size", + caches.l1d_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-line-size", + caches.l1d_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-sets", + caches.l1d_cache->sets); + qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-size", + caches.l1i_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-line-size", + caches.l1i_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-sets", + caches.l1i_cache->sets); + qemu_fdt_setprop_phandle(vms->fdt, nodename, "next-level-cache", + cachename); + g_free(cachename); +} + static void fdt_add_cpu_nodes(const VirtMachineState *vms) { int cpu; @@ -378,6 +461,11 @@ static void fdt_add_cpu_nodes(const VirtMachineState *= vms) qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); =20 + if (cpu_topology_enabled) { + fdt_add_l3cache_nodes(vms); + fdt_add_l2cache_nodes(vms); + } + for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); @@ -407,6 +495,9 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } =20 + if (cpu_topology_enabled) { + fdt_add_l1cache_prop(vms, nodename, cpu); + } qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", qemu_fdt_alloc_phandle(vms->fdt)); =20 --=20 2.23.0