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charset="utf-8" Signed-off-by: Ying Fang --- linux-headers/linux/kvm.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index a28c366737..461a2302e7 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1031,6 +1031,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SECURE_GUEST 181 #define KVM_CAP_HALT_POLL 182 #define KVM_CAP_ASYNC_PF_INT 183 +#define KVM_CAP_ARM_MP_AFFINITY 187 =20 #ifdef KVM_CAP_IRQ_ROUTING =20 @@ -1470,6 +1471,8 @@ struct kvm_s390_ucas_mapping { #define KVM_S390_SET_CMMA_BITS _IOW(KVMIO, 0xb9, struct kvm_s390_cmma= _log) /* Memory Encryption Commands */ #define KVM_MEMORY_ENCRYPT_OP _IOWR(KVMIO, 0xba, unsigned long) +/* Available with KVM_CAP_ARM_MP_AFFINITY */ +#define KVM_ARM_SET_MP_AFFINITY _IOWR(KVMIO, 0xbb, unsigned long) =20 struct kvm_enc_region { __u64 addr; --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 16 Sep 2020 20:23:47 -0700 (PDT) Received: from localhost ([::1]:48374 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kIkWQ-0007OT-5Q for importer@patchew.org; Wed, 16 Sep 2020 23:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47888) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkUP-0004yf-1g; Wed, 16 Sep 2020 23:21:41 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4699 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkUM-0004QM-Ev; Wed, 16 Sep 2020 23:21:40 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 7A375E32711B65A2A2E3; Thu, 17 Sep 2020 11:20:53 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:20:45 +0800 From: Ying Fang To: Subject: [RFC PATCH 02/12] target/arm/kvm64: make MPIDR consistent with CPU Topology Date: Thu, 17 Sep 2020 11:20:23 +0800 Message-ID: <20200917032033.2020-3-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=fangying1@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/16 23:20:53 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, zhang.zhanghailiang@huawei.com, alex.chen@huawei.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, alistair.francis@wdc.com, Ying Fang , imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" MPIDR helps to provide an additional PE identification in a multiprocessor system. This patch adds support for setting MPIDR from userspace, so that MPIDR is consistent with CPU topology configured. Signed-off-by: Ying Fang --- target/arm/kvm64.c | 46 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ef1e960285..fcce261a10 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -757,10 +757,46 @@ static int kvm_arm_sve_set_vls(CPUState *cs) =20 #define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5 =20 +static int kvm_arm_set_mp_affinity(CPUState *cs) +{ + uint64_t mpidr; + ARMCPU *cpu =3D ARM_CPU(cs); + + if (kvm_check_extension(kvm_state, KVM_CAP_ARM_MP_AFFINITY)) { + /* Make MPIDR consistent with CPU topology */ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + mpidr =3D (kvm_arch_vcpu_id(cs) % ms->smp.threads) << ARM_AFF0_SHI= FT; + mpidr |=3D ((kvm_arch_vcpu_id(cs) / ms->smp.threads % ms->smp.core= s) + & 0xff) << ARM_AFF1_SHIFT; + mpidr |=3D (kvm_arch_vcpu_id(cs) / (ms->smp.cores * ms->smp.thread= s) + & 0xff) << ARM_AFF2_SHIFT; + + /* Override mp affinity when KVM is in use */ + cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; + + /* Bit 31 is RES1 indicates the ARMv7 Multiprocessing Extensions */ + mpidr |=3D (1ULL << 31); + return kvm_vcpu_ioctl(cs, KVM_ARM_SET_MP_AFFINITY, &mpidr); + } else { + /* + * When KVM_CAP_ARM_MP_AFFINITY is not supported, it means KVM has= its + * own idea about MPIDR assignment, so we override our defaults wi= th + * what we get from KVM. + */ + int ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &= mpidr); + if (ret) { + error_report("failed to set MPIDR"); + return ret; + } + cpu->mp_affinity =3D mpidr & ARM32_AFFINITY_MASK; + return ret; + } +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret; - uint64_t mpidr; ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; =20 @@ -814,16 +850,10 @@ int kvm_arch_init_vcpu(CPUState *cs) } } =20 - /* - * When KVM is in use, PSCI is emulated in-kernel and not by qemu. - * Currently KVM has its own idea about MPIDR assignment, so we - * override our defaults with what we get from KVM. - */ - ret =3D kvm_get_one_reg(cs, ARM64_SYS_REG(ARM_CPU_ID_MPIDR), &mpidr); + ret =3D kvm_arm_set_mp_affinity(cs); if (ret) { return ret; } - cpu->mp_affinity =3D mpidr & ARM64_AFFINITY_MASK; =20 kvm_arm_init_debug(cs); =20 --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313049; cv=none; d=zohomail.com; s=zohoarc; b=IBEI7a4k8En/QLQbOLOhPy+G3/3V0E8QtDyQASmmxa0EiEGIhFBXvPMVm/FsrMymA+UrwizmHDRdSVB1w6fSaVeJIkkt0VAnc03+OWevderdyiA3rEdGJBvR+UbbAVgLJBgH3AH9PMvPXb7m/gV3R18QsyaSm3AiDF8U/m2CIfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313049; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jgeVGYbshpWer2hDY/pFw1nhul3o+auLHbF/R3jccv4=; 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Wed, 16 Sep 2020 23:21:42 -0400 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 31AAEAEDCE52875C0B5F; Thu, 17 Sep 2020 11:20:58 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:20:47 +0800 From: Ying Fang To: Subject: [RFC PATCH 03/12] target/arm/kvm32: make MPIDR consistent with CPU Topology Date: Thu, 17 Sep 2020 11:20:24 +0800 Message-ID: <20200917032033.2020-4-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.190; envelope-from=fangying1@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/16 23:20:53 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, zhang.zhanghailiang@huawei.com, alex.chen@huawei.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, alistair.francis@wdc.com, Ying Fang , imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" MPIDR helps to provide an additional PE identification in a multiprocessor system. This patch adds support for setting MPIDR from userspace, so that MPIDR is consistent with CPU topology configured. Signed-off-by: Ying Fang --- target/arm/kvm32.c | 46 ++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 38 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 0af46b41c8..85694dc8bf 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -201,11 +201,47 @@ int kvm_arm_cpreg_level(uint64_t regidx) =20 #define ARM_CPU_ID_MPIDR 0, 0, 0, 5 =20 +static int kvm_arm_set_mp_affinity(CPUState *cs) +{ + uint32_t mpidr; + ARMCPU *cpu =3D ARM_CPU(cs); + + if (kvm_check_extension(kvm_state, KVM_CAP_ARM_MP_AFFINITY)) { + /* Make MPIDR consistent with CPU topology */ + MachineState *ms =3D MACHINE(qdev_get_machine()); + + mpidr =3D (kvm_arch_vcpu_id(cs) % ms->smp.threads) << ARM_AFF0_SHI= FT; + mpidr |=3D ((kvm_arch_vcpu_id(cs) / ms->smp.threads % ms->smp.core= s) + & 0xff) << ARM_AFF1_SHIFT; + mpidr |=3D (kvm_arch_vcpu_id(cs) / (ms->smp.cores * ms->smp.thread= s) + & 0xff) << ARM_AFF2_SHIFT; + + /* Override mp affinity when KVM is in use */ + cpu->mp_affinity =3D mpidr & ARM32_AFFINITY_MASK; + + /* Bit 31 is RES1 indicates the ARMv7 Multiprocessing Extensions */ + mpidr |=3D (1ULL << 31); + return kvm_vcpu_ioctl(cs, KVM_ARM_SET_MP_AFFINITY, &mpidr); + } else { + /* + * When KVM_CAP_ARM_MP_AFFINITY is not supported, it means KVM has= its + * own idea about MPIDR assignment, so we override our defaults wi= th + * what we get from KVM. + */ + int ret =3D kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), = &mpidr); + if (ret) { + error_report("failed to set MPIDR"); + return ret; + } + cpu->mp_affinity =3D mpidr & ARM32_AFFINITY_MASK; + return ret; + } +} + int kvm_arch_init_vcpu(CPUState *cs) { int ret; uint64_t v; - uint32_t mpidr; struct kvm_one_reg r; ARMCPU *cpu =3D ARM_CPU(cs); =20 @@ -244,16 +280,10 @@ int kvm_arch_init_vcpu(CPUState *cs) return -EINVAL; } =20 - /* - * When KVM is in use, PSCI is emulated in-kernel and not by qemu. - * Currently KVM has its own idea about MPIDR assignment, so we - * override our defaults with what we get from KVM. - */ - ret =3D kvm_get_one_reg(cs, ARM_CP15_REG32(ARM_CPU_ID_MPIDR), &mpidr); + ret =3D kvm_arm_set_mp_affinity(cs); if (ret) { return ret; } - cpu->mp_affinity =3D mpidr & ARM32_AFFINITY_MASK; =20 /* Check whether userspace can specify guest syndrome value */ kvm_arm_init_serror_injection(cs); --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313006; cv=none; d=zohomail.com; s=zohoarc; b=AiTeQ+cf5+XA2ypmQY32vL+PZTUt8S7h0VB6Utg1QH6BgDiCtUMKQdrnolqnuUXKXmn7mjSIeAjXfH84i+Fe/jPJA94DEXhkDoYLa9kQFKQpVv6DJ12beemCOQUJkHCvwbiIHuj1DIj/BWi5613nQc7F/xTB3B0IqlxlirnzAqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313006; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 16 Sep 2020 23:21:40 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 876F151E885C02A826EF; Thu, 17 Sep 2020 11:20:58 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:20:49 +0800 From: Ying Fang To: Subject: [RFC PATCH 04/12] device_tree: add qemu_fdt_add_path Date: Thu, 17 Sep 2020 11:20:25 +0800 Message-ID: <20200917032033.2020-5-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" From: Andrew Jones qemu_fdt_add_path works like qemu_fdt_add_subnode, except it also recursively adds any missing parent nodes. Cc: Peter Crosthwaite Cc: Alexander Graf Signed-off-by: Andrew Jones --- device_tree.c | 24 ++++++++++++++++++++++++ include/sysemu/device_tree.h | 1 + 2 files changed, 25 insertions(+) diff --git a/device_tree.c b/device_tree.c index b335dae707..1854be3a02 100644 --- a/device_tree.c +++ b/device_tree.c @@ -524,6 +524,30 @@ int qemu_fdt_add_subnode(void *fdt, const char *name) return retval; } =20 +int qemu_fdt_add_path(void *fdt, const char *path) +{ + char *parent; + int offset; + + offset =3D fdt_path_offset(fdt, path); + if (offset < 0 && offset !=3D -FDT_ERR_NOTFOUND) { + error_report("%s Couldn't find node %s: %s", __func__, path, + fdt_strerror(offset)); + exit(1); + } + + if (offset !=3D -FDT_ERR_NOTFOUND) { + return offset; + } + + parent =3D g_strdup(path); + strrchr(parent, '/')[0] =3D '\0'; + qemu_fdt_add_path(fdt, parent); + g_free(parent); + + return qemu_fdt_add_subnode(fdt, path); +} + void qemu_fdt_dumpdtb(void *fdt, int size) { const char *dumpdtb =3D qemu_opt_get(qemu_get_machine_opts(), "dumpdtb= "); diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h index 982c89345f..15fb98af98 100644 --- a/include/sysemu/device_tree.h +++ b/include/sysemu/device_tree.h @@ -104,6 +104,7 @@ uint32_t qemu_fdt_get_phandle(void *fdt, const char *pa= th); uint32_t qemu_fdt_alloc_phandle(void *fdt); int qemu_fdt_nop_node(void *fdt, const char *node_path); int qemu_fdt_add_subnode(void *fdt, const char *name); +int qemu_fdt_add_path(void *fdt, const char *path); =20 #define qemu_fdt_setprop_cells(fdt, node_path, property, ...) = \ do { = \ --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313003; cv=none; d=zohomail.com; s=zohoarc; b=D0wmMQ0dElH9GqaVlvSnoXw9WAR5OO9bOUPvw3pbY3t8++EVPy9Xr/5t8mhtnpg5QZRqcKo8Wexh+1cW7DrW2168QgSs3BNO9HUk022isV+Nj7fuAb2ehQv+AvH9v5rMczRrRp0C3wDIxS7AlZVvDh2woX3ayIzLxFNA+m0C/Qw= ARC-Message-Signature: i=1; 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Wed, 16 Sep 2020 23:23:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47770) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkUM-0004uv-Ez; Wed, 16 Sep 2020 23:21:38 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:4701 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkTp-0004Qh-L7; Wed, 16 Sep 2020 23:21:38 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 98A92AAABFA1E255AFE5; Thu, 17 Sep 2020 11:20:59 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:20:51 +0800 From: Ying Fang To: Subject: [RFC PATCH 05/12] hw/arm/virt: DT: add cpu-map Date: Thu, 17 Sep 2020 11:20:26 +0800 Message-ID: <20200917032033.2020-6-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: Andrew Jones Support devicetree CPU topology descriptions. Signed-off-by: Andrew Jones --- hw/arm/virt.c | 37 ++++++++++++++++++++++++++++++++++++- include/hw/arm/virt.h | 1 + 2 files changed, 37 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index acf9bfbece..71f7dbb317 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -348,7 +348,10 @@ static void fdt_add_cpu_nodes(const VirtMachineState *= vms) int cpu; int addr_cells =3D 1; const MachineState *ms =3D MACHINE(vms); - + VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + unsigned int smp_cores =3D ms->smp.cores; + unsigned int smp_threads =3D ms->smp.threads; + bool cpu_topology_enabled =3D !vmc->ignore_cpu_topology; /* * From Documentation/devicetree/bindings/arm/cpus.txt * On ARM v8 64-bit systems value should be set to 2, @@ -404,8 +407,37 @@ static void fdt_add_cpu_nodes(const VirtMachineState *= vms) ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } =20 + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(vms->fdt)); + g_free(nodename); } + if (cpu_topology_enabled) { + /* Add vcpu topology by fdt node cpu-map. */ + qemu_fdt_add_subnode(vms->fdt, "/cpus/cpu-map"); + + for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { + char *cpu_path =3D g_strdup_printf("/cpus/cpu@%d", cpu); + char *map_path; + + if (smp_threads > 1) { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/%s%d/%s%d/%s%d", + "cluster", cpu / (smp_cores * smp_threads), + "core", (cpu / smp_threads) % smp_cores, + "thread", cpu % smp_threads); + } else { + map_path =3D g_strdup_printf( + "/cpus/cpu-map/%s%d/%s%d", + "cluster", cpu / smp_cores, + "core", cpu % smp_cores); + } + qemu_fdt_add_path(vms->fdt, map_path); + qemu_fdt_setprop_phandle(vms->fdt, map_path, "cpu", cpu_path); + g_free(map_path); + g_free(cpu_path); + } + } } =20 static void fdt_add_its_gic_node(VirtMachineState *vms) @@ -2553,8 +2585,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 2) =20 static void virt_machine_5_1_options(MachineClass *mc) { + VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + virt_machine_5_2_options(mc); compat_props_add(mc->compat_props, hw_compat_5_1, hw_compat_5_1_len); + vmc->ignore_cpu_topology =3D true; } DEFINE_VIRT_MACHINE(5, 1) =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index dff67e1bef..d37c6b7858 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -119,6 +119,7 @@ typedef struct { MachineClass parent; bool disallow_affinity_adjustment; bool no_its; + bool ignore_cpu_topology; bool no_pmu; bool claim_edge_triggered_timers; bool smbios_old_sys_ver; --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313185; cv=none; d=zohomail.com; s=zohoarc; b=UyG6L7LjgtUd2suBGjNJ+C7DuJEaWj0t6uwx3M306xMLxIqY4WJfrvimtNhzAqSzLXhFG1jiBptkKU/SUivXEGlHrkOBhwyZ+A/t6qkvkP/aHmgX46zSb0pSIMo18HXsTX0TLjtWucbBN3RqOLXQKzVXGxkPR/Ys6hvbSfNCWs0= ARC-Message-Signature: i=1; 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Wed, 16 Sep 2020 23:26:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47940) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkUR-00054e-DZ; Wed, 16 Sep 2020 23:21:43 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4747 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkUM-0004RL-LY; Wed, 16 Sep 2020 23:21:43 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D3C28BAC7ABDFF61A6C6; Thu, 17 Sep 2020 11:21:08 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:20:58 +0800 From: Ying Fang To: Subject: [RFC PATCH 06/12] hw/arm/virt-acpi-build: distinguish possible and present cpus Date: Thu, 17 Sep 2020 11:20:27 +0800 Message-ID: <20200917032033.2020-7-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" When building ACPI tables regarding CPUs we should always build them for the number of possible CPUs, not the number of present CPUs. We then ensure only the present CPUs are enabled. Signed-off-by: Andrew Jones Signed-off-by: Ying Fang --- hw/arm/virt-acpi-build.c | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 9efd7a3881..f1d574b5d3 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -56,14 +56,18 @@ =20 #define ARM_SPI_BASE 32 =20 -static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) +static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms) { uint16_t i; + CPUArchIdList *possible_cpus =3D MACHINE(vms)->possible_cpus; =20 - for (i =3D 0; i < smp_cpus; i++) { + for (i =3D 0; i < possible_cpus->len; i++) { Aml *dev =3D aml_device("C%.03X", i); aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007"))); aml_append(dev, aml_name_decl("_UID", aml_int(i))); + if (possible_cpus->cpus[i].cpu =3D=3D NULL) { + aml_append(dev, aml_name_decl("_STA", aml_int(0))); + } aml_append(scope, dev); } } @@ -635,6 +639,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) const int *irqmap =3D vms->irqmap; AcpiMadtGenericDistributor *gicd; AcpiMadtGenericMsiFrame *gic_msi; + int possible_cpus =3D MACHINE(vms)->possible_cpus->len; int i; =20 acpi_data_push(table_data, sizeof(AcpiMultipleApicTable)); @@ -645,7 +650,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicd->base_address =3D cpu_to_le64(memmap[VIRT_GIC_DIST].base); gicd->version =3D vms->gic_version; =20 - for (i =3D 0; i < vms->smp_cpus; i++) { + for (i =3D 0; i < possible_cpus; i++) { AcpiMadtGenericCpuInterface *gicc =3D acpi_data_push(table_data, sizeof(*gicc)); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); @@ -660,7 +665,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicc->cpu_interface_number =3D cpu_to_le32(i); gicc->arm_mpidr =3D cpu_to_le64(armcpu->mp_affinity); gicc->uid =3D cpu_to_le32(i); - gicc->flags =3D cpu_to_le32(ACPI_MADT_GICC_ENABLED); + if (i < vms->smp_cpus) { + gicc->flags =3D cpu_to_le32(ACPI_MADT_GICC_ENABLED); + } =20 if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) { gicc->performance_interrupt =3D cpu_to_le32(PPI(VIRTUAL_PMU_IR= Q)); @@ -764,7 +771,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) * the RTC ACPI device at all when using UEFI. */ scope =3D aml_scope("\\_SB"); - acpi_dsdt_add_cpus(scope, vms->smp_cpus); + acpi_dsdt_add_cpus(scope, vms); acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], (irqmap[VIRT_UART] + ARM_SPI_BASE)); if (vmc->acpi_expose_flash) { --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313187; cv=none; d=zohomail.com; s=zohoarc; b=l71DQPGVMaThv04l/Nz6VdAjprG5yw1hvT9r6Vu0Fd7/6BPLTYw7L8ReIlA1ICjeMUTZpBjZxHRR6+nifBDL+dQRdsdTSN6/l9WsH3TH5vIu/PsJD7D30Vy/KTZGudX6U4CYixsVE7jjlovsp0lpGrvFIW7nSwEVRffrqlbJmys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313187; 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Wed, 16 Sep 2020 23:21:43 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:53794 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kIkUM-0004RH-PU; Wed, 16 Sep 2020 23:21:42 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 6DF405B978E71AA35A9D; Thu, 17 Sep 2020 11:21:07 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:21:01 +0800 From: Ying Fang To: Subject: [RFC PATCH 07/12] hw/acpi/aml-build: add processor hierarchy node structure Date: Thu, 17 Sep 2020 11:20:28 +0800 Message-ID: <20200917032033.2020-8-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Add the processor hierarchy node structures to build ACPI information for CPU topology. Three helpers are introduced: (1) build_socket_hierarchy for socket description structure (2) build_processor_hierarchy for processor description structure (3) build_smt_hierarchy for thread (logic processor) description structure Signed-off-by: Ying Fang Signed-off-by: Henglong Fan --- hw/acpi/aml-build.c | 37 +++++++++++++++++++++++++++++++++++++ include/hw/acpi/aml-build.h | 7 +++++++ 2 files changed, 44 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index f6fbc9b95d..13eb6e1345 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1754,6 +1754,43 @@ void build_slit(GArray *table_data, BIOSLinker *link= er, MachineState *ms) table_data->len - slit_start, 1, NULL, NULL); } =20 +/* + * ACPI 6.3: 5.2.29.1 Processor hierarchy node structure (Type 0) + */ +void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id) +{ + build_append_byte(tbl, 0); /* Type 0 - processor */ + build_append_byte(tbl, 20); /* Length, no private resources */ + build_append_int_noprefix(tbl, 0, 2); /* Reserved */ + build_append_int_noprefix(tbl, 1, 4); /* Flags: Physical package */ + build_append_int_noprefix(tbl, parent, 4); /* Parent */ + build_append_int_noprefix(tbl, id, 4); /* ACPI processor ID */ + build_append_int_noprefix(tbl, 0, 4); /* Number of private resources = */ +} + +void build_processor_hierarchy(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id) +{ + build_append_byte(tbl, 0); /* Type 0 - processor */ + build_append_byte(tbl, 20); /* Length, no private resources */ + build_append_int_noprefix(tbl, 0, 2); /* Reserved */ + build_append_int_noprefix(tbl, flags, 4); /* Flags */ + build_append_int_noprefix(tbl, parent, 4); /* Parent */ + build_append_int_noprefix(tbl, id, 4); /* ACPI processor ID */ + build_append_int_noprefix(tbl, 0, 4); /* Number of private resources = */ +} + +void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id) +{ + build_append_byte(tbl, 0); /* Type 0 - processor */ + build_append_byte(tbl, 20); /* Length, add private resources= */ + build_append_int_noprefix(tbl, 0, 2); /* Reserved */ + build_append_int_noprefix(tbl, 0x0e, 4); /* Processor is a thread */ + build_append_int_noprefix(tbl, parent , 4); /* parent */ + build_append_int_noprefix(tbl, id, 4); /* ACPI processor ID */ + build_append_int_noprefix(tbl, 0, 4); /* Num of private resource= s */ +} + /* build rev1/rev3/rev5.1 FADT */ void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index d27da03d64..ff4c6a38f3 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -435,6 +435,13 @@ void build_srat_memory(AcpiSratMemoryAffinity *numamem= , uint64_t base, =20 void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms); =20 +void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id); + +void build_processor_hierarchy(GArray *tbl, uint32_t flags, + uint32_t parent, uint32_t id); + +void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id); + void build_fadt(GArray *tbl, BIOSLinker *linker, const AcpiFadtData *f, const char *oem_id, const char *oem_table_id); =20 --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313325; cv=none; d=zohomail.com; s=zohoarc; b=NgZDM40CYLQipmXlhQ5PCL8X4olS8XAEbIu/SukYccuqhoPh6XDm1UXAV3qUv2fGBUy4KVoA/39aiYbLIHrqDm8leKaeDExlXxumNUAbP7IlcRXCiBQz64HR1GT8slM0EtHrqxM/u+ceSIGUPSpcV+Ji/baOGLhvbi99BpZgWqE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313325; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YKniKsudMBoLA3nciAz+s8XTk82AfEjwd6cK+BUPct8=; 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Wed, 16 Sep 2020 23:21:45 -0400 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 3B6E6BB3E86ED2AFA745; Thu, 17 Sep 2020 11:21:14 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:21:02 +0800 From: Ying Fang To: Subject: [RFC PATCH 08/12] hw/arm/virt-acpi-build: add PPTT table Date: Thu, 17 Sep 2020 11:20:29 +0800 Message-ID: <20200917032033.2020-9-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Add the Processor Properties Topology Table (PPTT) to present CPU topology information to the guest. Signed-off-by: Andrew Jones Signed-off-by: Ying Fang --- hw/arm/virt-acpi-build.c | 42 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index f1d574b5d3..b5aa3d3c83 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -594,6 +594,42 @@ build_srat(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) "SRAT", table_data->len - srat_start, 3, NULL, NULL); } =20 +static void build_pptt(GArray *table_data, BIOSLinker *linker, MachineStat= e *ms) +{ + int pptt_start =3D table_data->len; + int uid =3D 0, cpus =3D 0, socket; + unsigned int smp_cores =3D ms->smp.cores; + unsigned int smp_threads =3D ms->smp.threads; + + acpi_data_push(table_data, sizeof(AcpiTableHeader)); + + for (socket =3D 0; cpus < ms->possible_cpus->len; socket++) { + uint32_t socket_offset =3D table_data->len - pptt_start; + int core; + + build_socket_hierarchy(table_data, 0, socket); + + for (core =3D 0; core < smp_cores; core++) { + uint32_t core_offset =3D table_data->len - pptt_start; + int thread; + + if (smp_threads <=3D 1) { + build_processor_hierarchy(table_data, 2, socket_offset, ui= d++); + } else { + build_processor_hierarchy(table_data, 0, socket_offset, co= re); + for (thread =3D 0; thread < smp_threads; thread++) { + build_smt_hierarchy(table_data, core_offset, uid++); + } + } + } + cpus +=3D smp_cores * smp_threads; + } + + build_header(linker, table_data, + (void *)(table_data->data + pptt_start), "PPTT", + table_data->len - pptt_start, 2, NULL, NULL); +} + /* GTDT */ static void build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) @@ -834,6 +870,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) unsigned dsdt, xsdt; GArray *tables_blob =3D tables->table_data; MachineState *ms =3D MACHINE(vms); + bool cpu_topology_enabled =3D !vmc->ignore_cpu_topology; =20 table_offsets =3D g_array_new(false, true /* clear */, sizeof(uint32_t)); @@ -853,6 +890,11 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) acpi_add_table(table_offsets, tables_blob); build_madt(tables_blob, tables->linker, vms); =20 + if (cpu_topology_enabled) { + acpi_add_table(table_offsets, tables_blob); + build_pptt(tables_blob, tables->linker, ms); + } + acpi_add_table(table_offsets, tables_blob); build_gtdt(tables_blob, tables->linker, vms); =20 --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313157; cv=none; d=zohomail.com; s=zohoarc; b=aGsK+vierGU9KfgRVdDYssstviwWaoasW0l23bRc58mBGmmeGAEQmXjxAbrRBNYTIwpE7vtwsZWzv8dd1Oc9PV7AHz+3f5HrSHgNxqgQeMvjXQf+9ZoW8EBtS/E1nskQWhxKe/EfSO0CdvmtKDZsYuScltS6HG8TLnGSR3qtpQE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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charset="utf-8" Add the CPUCacheInfo structure to hold CPU cache information for ARM cpus. A classic three level cache topology is used here. The default cache capacity is given and userspace can overwrite these values. Signed-off-by: Ying Fang --- target/arm/cpu.c | 42 ++++++++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 27 +++++++++++++++++++++++++++ 2 files changed, 69 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c179e0752d..efa8e1974a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -27,6 +27,7 @@ #include "qapi/visitor.h" #include "cpu.h" #include "internals.h" +#include "qemu/units.h" #include "exec/exec-all.h" #include "hw/qdev-properties.h" #if !defined(CONFIG_USER_ONLY) @@ -998,6 +999,45 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clusters= z) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } =20 +static CPUCaches default_cache_info =3D { + .l1d_cache =3D &(CPUCacheInfo) { + .type =3D DATA_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .line_size =3D 64, + .associativity =3D 4, + .sets =3D 256, + .attributes =3D 0x02, + }, + .l1i_cache =3D &(CPUCacheInfo) { + .type =3D INSTRUCTION_CACHE, + .level =3D 1, + .size =3D 64 * KiB, + .line_size =3D 64, + .associativity =3D 4, + .sets =3D 256, + .attributes =3D 0x04, + }, + .l2_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 2, + .size =3D 512 * KiB, + .line_size =3D 64, + .associativity =3D 8, + .sets =3D 1024, + .attributes =3D 0x0a, + }, + .l3_cache =3D &(CPUCacheInfo) { + .type =3D UNIFIED_CACHE, + .level =3D 3, + .size =3D 65536 * KiB, + .line_size =3D 64, + .associativity =3D 15, + .sets =3D 2048, + .attributes =3D 0x0a, + }, +}; + static void cpreg_hashtable_data_destroy(gpointer data) { /* @@ -1835,6 +1875,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } } =20 + cpu->caches =3D default_cache_info; + qemu_init_vcpu(cs); cpu_reset(cs); =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a1c7d8ebae..e9e3817e20 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -745,6 +745,30 @@ typedef enum ARMPSCIState { =20 typedef struct ARMISARegisters ARMISARegisters; =20 +/* Cache information type */ +enum CacheType { + DATA_CACHE, + INSTRUCTION_CACHE, + UNIFIED_CACHE +}; + +typedef struct CPUCacheInfo { + enum CacheType type; /* Cache Type*/ + uint8_t level; + uint32_t size; /* Size in bytes */ + uint16_t line_size; /* Line size in bytes */ + uint8_t associativity; /* Cache associativity */ + uint32_t sets; /* Number of sets */ + uint8_t attributes; /* Cache attributest */ +} CPUCacheInfo; + +typedef struct CPUCaches { + CPUCacheInfo *l1d_cache; + CPUCacheInfo *l1i_cache; + CPUCacheInfo *l2_cache; + CPUCacheInfo *l3_cache; +} CPUCaches; + /** * ARMCPU: * @env: #CPUARMState @@ -986,6 +1010,9 @@ struct ARMCPU { =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; + + /* CPU cache information */ + CPUCaches caches; }; =20 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu); --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313299; cv=none; d=zohomail.com; s=zohoarc; b=P5qfBq2PFkSki83kf9FKH72/jbyE6YDcWBWZbhHfZAblF3EWTl8yxZV3Wu9KiTxnVZxviyupCv+zVjSYys61wjWSYBxB60Uzs/xmEURLGJu/J2cbrn6qB0/81JhzkVreo7SabipfU3iiy521YzkgF2TbvMGS3Mr9INbkIq4qC5Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313299; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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charset="utf-8" Support devicetree CPU cache information descriptions Signed-off-by: Ying Fang --- hw/arm/virt.c | 91 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 71f7dbb317..74b748ae35 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -343,6 +343,89 @@ static void fdt_add_timer_nodes(const VirtMachineState= *vms) GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqfla= gs); } =20 +static void fdt_add_l3cache_nodes(const VirtMachineState *vms) +{ + int i; + const MachineState *ms =3D MACHINE(vms); + ARMCPU *cpu =3D ARM_CPU(first_cpu); + unsigned int smp_cores =3D ms->smp.cores; + unsigned int sockets =3D ms->smp.max_cpus / smp_cores; + + for (i =3D 0; i < sockets; i++) { + char *nodename =3D g_strdup_printf("/cpus/l3-cache%d", i); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cache"); + qemu_fdt_setprop_string(vms->fdt, nodename, "cache-unified", "true= "); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-level", 3); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-size", + cpu->caches.l3_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-line-size", + cpu->caches.l3_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-sets", + cpu->caches.l3_cache->sets); + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(vms->fdt)); + g_free(nodename); + } +} + +static void fdt_add_l2cache_nodes(const VirtMachineState *vms) +{ + int i, j; + const MachineState *ms =3D MACHINE(vms); + unsigned int smp_cores =3D ms->smp.cores; + signed int sockets =3D ms->smp.max_cpus / smp_cores; + ARMCPU *cpu =3D ARM_CPU(first_cpu); + + for (i =3D 0; i < sockets; i++) { + char *next_path =3D g_strdup_printf("/cpus/l3-cache%d", i); + for (j =3D 0; j < smp_cores; j++) { + char *nodename =3D g_strdup_printf("/cpus/l2-cache%d", + i * smp_cores + j); + qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cac= he"); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-size", + cpu->caches.l2_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-line-size", + cpu->caches.l2_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "cache-sets", + cpu->caches.l2_cache->sets); + qemu_fdt_setprop_phandle(vms->fdt, nodename, + "next-level-cache", next_path); + qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", + qemu_fdt_alloc_phandle(vms->fdt)); + g_free(nodename); + } + g_free(next_path); + } +} + +static void fdt_add_l1cache_prop(const VirtMachineState *vms, + char *nodename, int cpu_index) +{ + + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(cpu_index)); + CPUCaches caches =3D cpu->caches; + + char *cachename =3D g_strdup_printf("/cpus/l2-cache%d", cpu_index); + + qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-size", + caches.l1d_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-line-size", + caches.l1d_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "d-cache-sets", + caches.l1d_cache->sets); + qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-size", + caches.l1i_cache->size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-line-size", + caches.l1i_cache->line_size); + qemu_fdt_setprop_cell(vms->fdt, nodename, "i-cache-sets", + caches.l1i_cache->sets); + qemu_fdt_setprop_phandle(vms->fdt, nodename, "next-level-cache", + cachename); + g_free(cachename); +} + static void fdt_add_cpu_nodes(const VirtMachineState *vms) { int cpu; @@ -378,6 +461,11 @@ static void fdt_add_cpu_nodes(const VirtMachineState *= vms) qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); =20 + if (cpu_topology_enabled) { + fdt_add_l3cache_nodes(vms); + fdt_add_l2cache_nodes(vms); + } + for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); @@ -407,6 +495,9 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } =20 + if (cpu_topology_enabled) { + fdt_add_l1cache_prop(vms, nodename, cpu); + } qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", qemu_fdt_alloc_phandle(vms->fdt)); =20 --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313410; cv=none; d=zohomail.com; s=zohoarc; b=IIe29z/jeD79LU5YX+R6oonkn5VTj+8W62L4ghedj5Wk71SOIfGlZPWNjop9TwXMN+Qq+1EOi29gpARexLpfERHnP1naJ0Sc/asYIzXFl7Bs7SXF0RXrwnt5G3K1CBRO9IjTcbdRocas8r4GVrkmImytM0CtYDsBbW5473Jx8LE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313410; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 16 Sep 2020 23:21:47 -0400 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 9A6A556C8413BBCE50E3; Thu, 17 Sep 2020 11:21:15 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:21:06 +0800 From: Ying Fang To: Subject: [RFC PATCH 11/12] hw/acpi/aml-build: build ACPI CPU cache topology information Date: Thu, 17 Sep 2020 11:20:32 +0800 Message-ID: <20200917032033.2020-12-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" To build cache information, An AcpiCacheInfo structure is defined to hold the Type 1 cache structure according to ACPI spec v6.3 5.2.29.2. A helper function build_cache_hierarchy is introduced to encode the cache information. Signed-off-by: Ying Fang --- hw/acpi/aml-build.c | 26 ++++++++++++++++++++++++++ include/hw/acpi/acpi-defs.h | 8 ++++++++ include/hw/acpi/aml-build.h | 3 +++ 3 files changed, 37 insertions(+) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 13eb6e1345..123eb032cd 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1754,6 +1754,32 @@ void build_slit(GArray *table_data, BIOSLinker *link= er, MachineState *ms) table_data->len - slit_start, 1, NULL, NULL); } =20 +/* ACPI 6.3: 5.29.2 Cache type structure (Type 1) */ +static void build_cache_head(GArray *tbl, uint32_t next_level) +{ + build_append_byte(tbl, 1); + build_append_byte(tbl, 24); + build_append_int_noprefix(tbl, 0, 2); + build_append_int_noprefix(tbl, 0x7f, 4); + build_append_int_noprefix(tbl, next_level, 4); +} + +static void build_cache_tail(GArray *tbl, AcpiCacheInfo *cache_info) +{ + build_append_int_noprefix(tbl, cache_info->size, 4); + build_append_int_noprefix(tbl, cache_info->sets, 4); + build_append_byte(tbl, cache_info->associativity); + build_append_byte(tbl, cache_info->attributes); + build_append_int_noprefix(tbl, cache_info->line_size, 2); +} + +void build_cache_hierarchy(GArray *tbl, + uint32_t next_level, AcpiCacheInfo *cache_info) +{ + build_cache_head(tbl, next_level); + build_cache_tail(tbl, cache_info); +} + /* * ACPI 6.3: 5.2.29.1 Processor hierarchy node structure (Type 0) */ diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 38a42f409a..3df38ab449 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -618,4 +618,12 @@ struct AcpiIortRC { } QEMU_PACKED; typedef struct AcpiIortRC AcpiIortRC; =20 +typedef struct AcpiCacheInfo { + uint32_t size; + uint32_t sets; + uint8_t associativity; + uint8_t attributes; + uint16_t line_size; +} AcpiCacheInfo; + #endif diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index ff4c6a38f3..ced1ae6a83 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -435,6 +435,9 @@ void build_srat_memory(AcpiSratMemoryAffinity *numamem,= uint64_t base, =20 void build_slit(GArray *table_data, BIOSLinker *linker, MachineState *ms); =20 +void build_cache_hierarchy(GArray *tbl, + uint32_t next_level, AcpiCacheInfo *cache_info); + void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id); =20 void build_processor_hierarchy(GArray *tbl, uint32_t flags, --=20 2.23.0 From nobody Mon May 6 14:47:09 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1600313435; cv=none; d=zohomail.com; s=zohoarc; b=WTCDPLKMp5SeTBp2Fo1MD1GBYRyMhKwVNzuwMrqjCx49emqahkUfF6rjlUb6tHhOw26l+Wd7eMOkhhsLMPvy8bp+uVtDT/6y7OMse5q7twKdQgllWc3LTCGl+9VvytFXvnHsY1858cGaspA3EWyLG3tQzmSjlh8eeQgBwr3sA2c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600313435; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 16 Sep 2020 23:21:43 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 05F8EEB1067D628429A8; Thu, 17 Sep 2020 11:21:18 +0800 (CST) Received: from localhost (10.174.185.104) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.487.0; Thu, 17 Sep 2020 11:21:07 +0800 From: Ying Fang To: Subject: [RFC PATCH 12/12] hw/arm/virt-acpi-build: Enable CPU cache topology Date: Thu, 17 Sep 2020 11:20:33 +0800 Message-ID: <20200917032033.2020-13-fangying1@huawei.com> X-Mailer: git-send-email 2.26.0.windows.1 In-Reply-To: <20200917032033.2020-1-fangying1@huawei.com> References: <20200917032033.2020-1-fangying1@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.174.185.104] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=fangying1@huawei.com; helo=huawei.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/16 23:20:51 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, zhang.zhanghailiang@huawei.com, Henglong Fan , alex.chen@huawei.com, shannon.zhaosl@gmail.com, qemu-arm@nongnu.org, alistair.francis@wdc.com, Ying Fang , imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" A helper struct AcpiCacheOffset is introduced to describe the offset of three level caches. The cache hierarchy is built according to ACPI spec v6.3 5.2.29.2. Let's enable CPU cache topology now. Signed-off-by: Ying Fang Signed-off-by: Henglong Fan --- hw/acpi/aml-build.c | 19 +++++++++----- hw/arm/virt-acpi-build.c | 52 ++++++++++++++++++++++++++++++++----- include/hw/acpi/acpi-defs.h | 6 +++++ include/hw/acpi/aml-build.h | 7 ++--- 4 files changed, 68 insertions(+), 16 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 123eb032cd..f8d74f3f10 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -1783,27 +1783,32 @@ void build_cache_hierarchy(GArray *tbl, /* * ACPI 6.3: 5.2.29.1 Processor hierarchy node structure (Type 0) */ -void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id) +void build_socket_hierarchy(GArray *tbl, uint32_t parent, + uint32_t offset, uint32_t id) { build_append_byte(tbl, 0); /* Type 0 - processor */ - build_append_byte(tbl, 20); /* Length, no private resources */ + build_append_byte(tbl, 24); /* Length, no private resources */ build_append_int_noprefix(tbl, 0, 2); /* Reserved */ build_append_int_noprefix(tbl, 1, 4); /* Flags: Physical package */ build_append_int_noprefix(tbl, parent, 4); /* Parent */ build_append_int_noprefix(tbl, id, 4); /* ACPI processor ID */ - build_append_int_noprefix(tbl, 0, 4); /* Number of private resources = */ + build_append_int_noprefix(tbl, 1, 4); /* Number of private resources= */ + build_append_int_noprefix(tbl, offset, 4); /* Private resources */ } =20 -void build_processor_hierarchy(GArray *tbl, uint32_t flags, - uint32_t parent, uint32_t id) +void build_processor_hierarchy(GArray *tbl, uint32_t flags, uint32_t paren= t, + AcpiCacheOffset offset, uint32_t id) { build_append_byte(tbl, 0); /* Type 0 - processor */ - build_append_byte(tbl, 20); /* Length, no private resources */ + build_append_byte(tbl, 32); /* Length, no private resources */ build_append_int_noprefix(tbl, 0, 2); /* Reserved */ build_append_int_noprefix(tbl, flags, 4); /* Flags */ build_append_int_noprefix(tbl, parent, 4); /* Parent */ build_append_int_noprefix(tbl, id, 4); /* ACPI processor ID */ - build_append_int_noprefix(tbl, 0, 4); /* Number of private resources = */ + build_append_int_noprefix(tbl, 3, 4); /* Number of private resources = */ + build_append_int_noprefix(tbl, offset.l1d_offset, 4);/* Private resour= ces */ + build_append_int_noprefix(tbl, offset.l1i_offset, 4);/* Private resour= ces */ + build_append_int_noprefix(tbl, offset.l2_offset, 4); /* Private resour= ces */ } =20 void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index b5aa3d3c83..375fb9e24f 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -594,29 +594,69 @@ build_srat(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) "SRAT", table_data->len - srat_start, 3, NULL, NULL); } =20 -static void build_pptt(GArray *table_data, BIOSLinker *linker, MachineStat= e *ms) +static inline void arm_acpi_cache_info(CPUCacheInfo *cpu_cache, + AcpiCacheInfo *acpi_cache) { + acpi_cache->size =3D cpu_cache->size; + acpi_cache->sets =3D cpu_cache->sets; + acpi_cache->associativity =3D cpu_cache->associativity; + acpi_cache->attributes =3D cpu_cache->attributes; + acpi_cache->line_size =3D cpu_cache->line_size; +} + +static void build_pptt(GArray *table_data, BIOSLinker *linker, + VirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); int pptt_start =3D table_data->len; int uid =3D 0, cpus =3D 0, socket; unsigned int smp_cores =3D ms->smp.cores; unsigned int smp_threads =3D ms->smp.threads; + AcpiCacheOffset offset; + ARMCPU *cpu =3D ARM_CPU(qemu_get_cpu(cpus)); + AcpiCacheInfo cache_info; =20 acpi_data_push(table_data, sizeof(AcpiTableHeader)); =20 for (socket =3D 0; cpus < ms->possible_cpus->len; socket++) { - uint32_t socket_offset =3D table_data->len - pptt_start; + uint32_t l3_offset =3D table_data->len - pptt_start; + uint32_t socket_offset; int core; =20 - build_socket_hierarchy(table_data, 0, socket); + /* L3 cache type structure */ + arm_acpi_cache_info(cpu->caches.l3_cache, &cache_info); + build_cache_hierarchy(table_data, 0, &cache_info); + + socket_offset =3D table_data->len - pptt_start; + build_socket_hierarchy(table_data, 0, l3_offset, socket); =20 for (core =3D 0; core < smp_cores; core++) { uint32_t core_offset =3D table_data->len - pptt_start; int thread; =20 + /* L2 cache tpe structure */ + offset.l2_offset =3D table_data->len - pptt_start; + arm_acpi_cache_info(cpu->caches.l2_cache, &cache_info); + build_cache_hierarchy(table_data, 0, &cache_info); + + /* L1d cache type structure */ + offset.l1d_offset =3D table_data->len - pptt_start; + arm_acpi_cache_info(cpu->caches.l1d_cache, &cache_info); + build_cache_hierarchy(table_data, offset.l2_offset, &cache_inf= o); + + /* L1i cache type structure */ + offset.l1i_offset =3D table_data->len - pptt_start; + arm_acpi_cache_info(cpu->caches.l1i_cache, &cache_info); + build_cache_hierarchy(table_data, offset.l2_offset, &cache_inf= o); + + core_offset =3D table_data->len - pptt_start; if (smp_threads <=3D 1) { - build_processor_hierarchy(table_data, 2, socket_offset, ui= d++); + build_processor_hierarchy(table_data, 2, socket_offset, + offset, uid++); } else { - build_processor_hierarchy(table_data, 0, socket_offset, co= re); + + build_processor_hierarchy(table_data, 0, socket_offset, + offset, core); for (thread =3D 0; thread < smp_threads; thread++) { build_smt_hierarchy(table_data, core_offset, uid++); } @@ -892,7 +932,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) =20 if (cpu_topology_enabled) { acpi_add_table(table_offsets, tables_blob); - build_pptt(tables_blob, tables->linker, ms); + build_pptt(tables_blob, tables->linker, vms); } =20 acpi_add_table(table_offsets, tables_blob); diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 3df38ab449..e48b7fa506 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -626,4 +626,10 @@ typedef struct AcpiCacheInfo { uint16_t line_size; } AcpiCacheInfo; =20 +typedef struct AcpiCacheOffset { + uint32_t l1d_offset; + uint32_t l1i_offset; + uint32_t l2_offset; +} AcpiCacheOffset; + #endif diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index ced1ae6a83..984c5dec3b 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -438,10 +438,11 @@ void build_slit(GArray *table_data, BIOSLinker *linke= r, MachineState *ms); void build_cache_hierarchy(GArray *tbl, uint32_t next_level, AcpiCacheInfo *cache_info); =20 -void build_socket_hierarchy(GArray *tbl, uint32_t parent, uint32_t id); +void build_socket_hierarchy(GArray *tbl, uint32_t parent, + uint32_t offset, uint32_t id); =20 -void build_processor_hierarchy(GArray *tbl, uint32_t flags, - uint32_t parent, uint32_t id); +void build_processor_hierarchy(GArray *tbl, uint32_t flags, uint32_t paren= t, + AcpiCacheOffset offset, uint32_t id); =20 void build_smt_hierarchy(GArray *tbl, uint32_t parent, uint32_t id); =20 --=20 2.23.0