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[83.57.170.65]) by smtp.gmail.com with ESMTPSA id d6sm35474850wrq.67.2020.09.16.13.40.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2020 13:40:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1600288815; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=iV/ElKucvX82AYjveXxyl1sOCENXpVHeSTvARkSKpI4=; b=GzUAbqvkBapxooNEQm47EEdX2CqYevCH992Fzoq6Bp/DFjlfjsacWNFaK8NBj3VrYo+pWe /OorasKjUxZH5jpzTxFiNXtJZpzh+mKSC+pI5p9r2QVZZ6tYiRAvmAooJPfdSsePiWAU3I lkvP105ki9S/k/1xAmFWadBBGeXqSVo= X-MC-Unique: jPMl_uhuM9SdtyTACOimpQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iV/ElKucvX82AYjveXxyl1sOCENXpVHeSTvARkSKpI4=; b=Kq3MDChK7ZcJM2+JO3Rj+uQIawR55swrhIVe+1ZQ2mY/Qan3mLAlN9f++QJhpIzJe3 UJxfg3L37kkVGof0vR7S4CTvabApnh7wHOG+5MHQl6dPk0EPIDwlcUiZy5VFF4IORxlw DHqXEa9sY7LmY0Mx0onLFxJLTNwa6RN/EibqgtNbx0SkgWfzoidDy1DEFdq666RunAbY hdmdkZWxBS+KZbDUmKEskGBa8vZZkWVac4BlqRVAFZYRyFs/kbZHReIwgT93N7ZcbsdN OhzQ1LNUpBe3HGRI3OmESZvT33YFBSwL3gsDrPEEPk1bFHSnAzohWzVhosHi70xLSOou GqfA== X-Gm-Message-State: AOAM531PMMyrTJ+/vPcSrdcn82tJXlY/o3vpRTKJmpPTdLmYgB9HpBis sHrJ+6bMm9uIl8GzUJGrNUCbAHn7Ifjz57aHIhvNVTkkP5dF7VetnH/CgxgP7B0H35fg7uAyXKe 1O+foyWGp9/EuRA== X-Received: by 2002:a1c:f715:: with SMTP id v21mr7039785wmh.117.1600288811945; Wed, 16 Sep 2020 13:40:11 -0700 (PDT) X-Google-Smtp-Source: ABdhPJz0BRSKUk1/BHT7jquOHQu/rHGGRcmepdVQVvD/tPFjMeB7ZqbrnLPBFIgCzuuH4wtZxUTP+Q== X-Received: by 2002:a1c:f715:: with SMTP id v21mr7039762wmh.117.1600288811765; Wed, 16 Sep 2020 13:40:11 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fam Zheng , Kevin Wolf , Max Reitz , qemu-block@nongnu.org, Stefan Hajnoczi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/3] block/nvme: Initialize constant values with const_le32() Date: Wed, 16 Sep 2020 22:40:02 +0200 Message-Id: <20200916204004.1511985-2-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200916204004.1511985-1-philmd@redhat.com> References: <20200916204004.1511985-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0.003 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) To avoid multiple endianess conversion, as we know the device registers are in little-endian, directly use const_le32() with constant values. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index f4f27b6da7d..b91749713e0 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -511,7 +511,7 @@ static void nvme_identify(BlockDriverState *bs, int nam= espace, Error **errp) uint64_t iova; NvmeCmd cmd =3D { .opcode =3D NVME_ADM_CMD_IDENTIFY, - .cdw10 =3D cpu_to_le32(0x1), + .cdw10 =3D const_le32(0x1), }; =20 id =3D qemu_try_memalign(s->page_size, sizeof(*id)); @@ -649,7 +649,7 @@ static bool nvme_add_io_queue(BlockDriverState *bs, Err= or **errp) .opcode =3D NVME_ADM_CMD_CREATE_CQ, .dptr.prp1 =3D cpu_to_le64(q->cq.iova), .cdw10 =3D cpu_to_le32(((queue_size - 1) << 16) | (n & 0xFFFF)), - .cdw11 =3D cpu_to_le32(0x3), + .cdw11 =3D const_le32(0x3), }; if (nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd)) { error_setg(errp, "Failed to create CQ io queue [%d]", n); @@ -734,10 +734,10 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, timeout_ms =3D MIN(500 * ((cap >> 24) & 0xFF), 30000); =20 /* Reset device to get a clean state. */ - s->regs->ctrl.cc =3D cpu_to_le32(le32_to_cpu(s->regs->ctrl.cc) & 0xFE); + s->regs->ctrl.cc &=3D const_le32(0xFE); /* Wait for CSTS.RDY =3D 0. */ deadline =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCA= LE_MS; - while (le32_to_cpu(s->regs->ctrl.csts) & 0x1) { + while (s->regs->ctrl.csts & const_le32(0x1)) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to reset (%" PRId64 " ms)", @@ -758,18 +758,18 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); - s->regs->ctrl.aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE= _SIZE); + s->regs->ctrl.aqa =3D const_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_= SIZE); s->regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); s->regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); =20 /* After setting up all control registers we can enable device now. */ - s->regs->ctrl.cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | + s->regs->ctrl.cc =3D const_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 0x1); /* Wait for CSTS.RDY =3D 1. */ now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); deadline =3D now + timeout_ms * 1000000; - while (!(le32_to_cpu(s->regs->ctrl.csts) & 0x1)) { + while (!(s->regs->ctrl.csts & const_le32(0x1))) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to start (%" PRId64 " ms)", @@ -848,8 +848,8 @@ static int nvme_enable_disable_write_cache(BlockDriverS= tate *bs, bool enable, NvmeCmd cmd =3D { .opcode =3D NVME_ADM_CMD_SET_FEATURES, .nsid =3D cpu_to_le32(s->nsid), - .cdw10 =3D cpu_to_le32(0x06), - .cdw11 =3D cpu_to_le32(enable ? 0x01 : 0x00), + .cdw10 =3D const_le32(0x06), + .cdw11 =3D enable ? const_le32(0x01) : 0x00, }; =20 ret =3D nvme_cmd_sync(bs, s->queues[INDEX_ADMIN], &cmd); @@ -1278,8 +1278,8 @@ static int coroutine_fn nvme_co_pdiscard(BlockDriverS= tate *bs, NvmeCmd cmd =3D { .opcode =3D NVME_CMD_DSM, .nsid =3D cpu_to_le32(s->nsid), - .cdw10 =3D cpu_to_le32(0), /*number of ranges - 0 based*/ - .cdw11 =3D cpu_to_le32(1 << 2), /*deallocate bit*/ + .cdw10 =3D const_le32(0), /*number of ranges - 0 based*/ + .cdw11 =3D const_le32(1 << 2), /*deallocate bit*/ }; =20 NVMeCoData data =3D { --=20 2.26.2 From nobody Mon Apr 29 06:15:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) client-ip=216.205.24.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1600288821; cv=none; d=zohomail.com; s=zohoarc; b=Vw5o3d1nJ/fQXF6b58FlWUpTjbpuQR957WmB3UaXa0Pai3XYVQo3drv9qkrlf7lDwy5p0aS4Wtt6HhK87ZnLCZjisQ93uxRErwNuOdtZNqQ559+K8FjrbHb13RYqi4AKMDoMn01ki9SZ/eWzshbjt6rtuD0zJHYsW472pz7tZ6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600288821; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=qm07GWZnH+HjHqIDhmqiLd8bzLDbx2r61BRcywFirDc=; b=j0qGWffJuEfLN8II21J4MudpGh/V98YZqjKPlsv1vVR1CsCciO2yAxTZijdZEO78rryvVMr6+HIoHgTXKXC0R37kIXisKMtP7x7hbrd8pms5wA/CL0N6uVW4kA/iIatAOTpEO9tCLxSmEy4IDyUeQJB/Pjny952vAzINE4jEKZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 216.205.24.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) header.from= Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [216.205.24.124]) by mx.zohomail.com with SMTPS id 160028882146776.64472546815216; Wed, 16 Sep 2020 13:40:21 -0700 (PDT) Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-275-7lQddRM-MwmPfT5ehMRBuQ-1; Wed, 16 Sep 2020 16:40:18 -0400 Received: by mail-wr1-f72.google.com with SMTP id j7so3011793wro.14 for ; Wed, 16 Sep 2020 13:40:18 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (65.red-83-57-170.dynamicip.rima-tde.net. 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David Alan Gilbert" Subject: [PATCH 2/3] block/nvme: Use atomic operations instead of 'volatile' keyword Date: Wed, 16 Sep 2020 22:40:03 +0200 Message-Id: <20200916204004.1511985-3-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200916204004.1511985-1-philmd@redhat.com> References: <20200916204004.1511985-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0.003 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) Follow docs/devel/atomics.rst guidelines and use atomic operations. Cc: Paolo Bonzini Cc: Richard Henderson Cc: Dr. David Alan Gilbert Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index b91749713e0..be80ea1f410 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -46,7 +46,7 @@ typedef struct { uint8_t *queue; uint64_t iova; /* Hardware MMIO register */ - volatile uint32_t *doorbell; + uint32_t *doorbell; } NVMeQueue; =20 typedef struct { @@ -82,7 +82,7 @@ typedef struct { } NVMeQueuePair; =20 /* Memory mapped registers */ -typedef volatile struct { +typedef struct { NvmeBar ctrl; struct { uint32_t sq_tail; @@ -273,8 +273,7 @@ static void nvme_kick(NVMeQueuePair *q) trace_nvme_kick(s, q->index); assert(!(q->sq.tail & 0xFF00)); /* Fence the write to submission queue entry before notifying the devi= ce. */ - smp_wmb(); - *q->sq.doorbell =3D cpu_to_le32(q->sq.tail); + atomic_rcu_set(q->sq.doorbell, cpu_to_le32(q->sq.tail)); q->inflight +=3D q->need_kick; q->need_kick =3D 0; } @@ -414,8 +413,7 @@ static bool nvme_process_completion(NVMeQueuePair *q) } if (progress) { /* Notify the device so it can post more completions. */ - smp_mb_release(); - *q->cq.doorbell =3D cpu_to_le32(q->cq.head); + atomic_store_release(q->cq.doorbell, cpu_to_le32(q->cq.head)); nvme_wake_free_req_locked(q); } =20 @@ -433,8 +431,7 @@ static void nvme_process_completion_bh(void *opaque) * called aio_poll(). The callback may be waiting for further completi= ons * so notify the device that it has space to fill in more completions = now. */ - smp_mb_release(); - *q->cq.doorbell =3D cpu_to_le32(q->cq.head); + atomic_store_release(q->cq.doorbell, cpu_to_le32(q->cq.head)); nvme_wake_free_req_locked(q); =20 nvme_process_completion(q); @@ -721,7 +718,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, /* Perform initialize sequence as described in NVMe spec "7.6.1 * Initialization". */ =20 - cap =3D le64_to_cpu(s->regs->ctrl.cap); + cap =3D le64_to_cpu(atomic_read(&s->regs->ctrl.cap)); if (!(cap & (1ULL << 37))) { error_setg(errp, "Device doesn't support NVMe command set"); ret =3D -EINVAL; @@ -734,10 +731,11 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, timeout_ms =3D MIN(500 * ((cap >> 24) & 0xFF), 30000); =20 /* Reset device to get a clean state. */ - s->regs->ctrl.cc &=3D const_le32(0xFE); + atomic_set(&s->regs->ctrl.cc, + cpu_to_le32(atomic_read(&s->regs->ctrl.cc) & const_le32(0xF= E))); /* Wait for CSTS.RDY =3D 0. */ deadline =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCA= LE_MS; - while (s->regs->ctrl.csts & const_le32(0x1)) { + while (atomic_read(&s->regs->ctrl.csts) & const_le32(0x1)) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to reset (%" PRId64 " ms)", @@ -758,18 +756,22 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); - s->regs->ctrl.aqa =3D const_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_= SIZE); - s->regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); - s->regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); + atomic_set(&s->regs->ctrl.aqa, + const_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE)); + atomic_set(&s->regs->ctrl.asq, + cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova)); + atomic_set(&s->regs->ctrl.acq, + cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova)); =20 /* After setting up all control registers we can enable device now. */ - s->regs->ctrl.cc =3D const_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | - (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | - 0x1); + atomic_set(&s->regs->ctrl.cc, + const_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | + (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | + 0x1)); /* Wait for CSTS.RDY =3D 1. */ now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); deadline =3D now + timeout_ms * 1000000; - while (!(s->regs->ctrl.csts & const_le32(0x1))) { + while (!(atomic_read(&s->regs->ctrl.csts) & const_le32(0x1))) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to start (%" PRId64 " ms)", --=20 2.26.2 From nobody Mon Apr 29 06:15:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) client-ip=63.128.21.124; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-124.mimecast.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1600288826; cv=none; d=zohomail.com; s=zohoarc; b=ONyKv/FVgjt35K75riX8LS9X6ZfV6xTP8mBO8TuwLYdxbPAyUL3GFuoQndLoua95tIoYBiw2iQn0fItAvNYq7nz1+i/1sbCBeQs66J/z4ZRbBsXTJyOdr0pUEcKwKyAjRaUQldyQl7bq7r9ROzAaKoe5U/t6Z0XEJsdi5iMWHkA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600288826; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=5dfg09EHj5Ati1T5gFLGt5bazj5HbyhTa8QLgR4w0EM=; b=ZXB9jr6mAQpsLS1yCDgNKQoqFWWmxsm+lpTJoqoFZkQ6beRmgIWROjx9NwtZgIK6QP1mLpt3Re5IHIAPqZcP96KtWo3yANEWt3s0rXjDY81OOLdqbDO4KMxzD8bPH5SdfCmqTBTaN1XSs8lX5xGHZZAlE06gU0dmSFiA4csISaQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of redhat.com designates 63.128.21.124 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) header.from= Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [63.128.21.124]) by mx.zohomail.com with SMTPS id 1600288826516305.52220085980707; Wed, 16 Sep 2020 13:40:26 -0700 (PDT) Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-308-12Mr322WOEmgeFUMPl0ruw-1; Wed, 16 Sep 2020 16:40:23 -0400 Received: by mail-wm1-f71.google.com with SMTP id x81so1462451wmg.8 for ; Wed, 16 Sep 2020 13:40:23 -0700 (PDT) Return-Path: Return-Path: Received: from x1w.redhat.com (65.red-83-57-170.dynamicip.rima-tde.net. [83.57.170.65]) by smtp.gmail.com with ESMTPSA id c14sm27424529wrm.64.2020.09.16.13.40.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Sep 2020 13:40:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1600288825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5dfg09EHj5Ati1T5gFLGt5bazj5HbyhTa8QLgR4w0EM=; b=VoameEtr0tZlAT3TTSySzRJrjz/DJ3EKqnKtg9CBJ7ZFNcIOFoGvqO5NvUuXH3tjLO7GCp 9AjwBUVa+7T+g3JVCKLlUjJeRgGD/DNJif1tRizqhQL9WYcjQj9i4E2mchMbsdPXRGX4Sv AsxIXhOvU79yE25K0O7AFmmExvbIA3k= X-MC-Unique: 12Mr322WOEmgeFUMPl0ruw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5dfg09EHj5Ati1T5gFLGt5bazj5HbyhTa8QLgR4w0EM=; b=orAxyO9WWsRSckAve0pYVJyeMSv3+iYj1ks56KYQkbj8BQueG9sUjNmwyjVEmZpyeV FRtzBDb/0JzBo+jgP+52AaYk/eRFCmjcMImbl+0kUkAeDi12e2tp55LekHMpygoA7NRS RpwSgAbdfql7lO4NwQsOKwLFKfRstujDzxqAD+Zj1lwu47mbjPBVLRvKETZPtsMOfzEC 7KroJNmmtnKKQ+uAzXXyqz+8VYEmKJ8jHyg/VlLyuEG6MXc//lcX3XY1tFtyzvkg3hME 6ePdFZFU5GbPLvT75AYl9lf1+0N0A1BufWNtqlKy13oQSRQK3Y/hqDOFtKdZdnazPQC4 PnUw== X-Gm-Message-State: AOAM533SlhIqYF8BHJPD7NRHmCWdfwaNixMuKwf/19TVVaS1hkxn1sPu KV3QyncB2sSWzJJO0YFmzdy8N/dl498pasoYaLTyA5aCry7aCOkDKAn/2VWOPP7TSemIuz1p8bu wKSNmm9mSMG0N+w== X-Received: by 2002:a7b:ca56:: with SMTP id m22mr6189485wml.12.1600288822608; Wed, 16 Sep 2020 13:40:22 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwjWbMmuJceCnFQDrGpD02GAKDl/p1/zQd5pK1QMUdRT0pzVXEffjd6g682HXYmfxCPwgwGXg== X-Received: by 2002:a7b:ca56:: with SMTP id m22mr6189478wml.12.1600288822462; Wed, 16 Sep 2020 13:40:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Fam Zheng , Kevin Wolf , Max Reitz , qemu-block@nongnu.org, Stefan Hajnoczi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 3/3] block/nvme: Align NVMeRegs structure to 4KiB and mark it packed Date: Wed, 16 Sep 2020 22:40:04 +0200 Message-Id: <20200916204004.1511985-4-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200916204004.1511985-1-philmd@redhat.com> References: <20200916204004.1511985-1-philmd@redhat.com> MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=philmd@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @redhat.com) In commit e5ff22ba9fc we changed the doorbells register declaration but forgot to mark the structure packed (as MMIO registers), allowing the compiler to optimize it. Fix by marking it packed, and align it to avoid: block/nvme.c: In function =E2=80=98nvme_create_queue_pair=E2=80=99: block/nvme.c:252:22: error: taking address of packed member of =E2=80=98s= truct =E2=80=99 may result in an unaligned pointer value [-Werro= r=3Daddress-of-packed-member] 252 | q->sq.doorbell =3D &s->regs->doorbells[idx * s->doorbell_sc= ale].sq_tail; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~= ~~~~~~~~~~ Fixes: e5ff22ba9fc ("block/nvme: Pair doorbell registers") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index be80ea1f410..2f9f560ccd5 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -12,6 +12,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" #include #include "qapi/error.h" #include "qapi/qmp/qdict.h" @@ -82,13 +83,15 @@ typedef struct { } NVMeQueuePair; =20 /* Memory mapped registers */ -typedef struct { +typedef struct QEMU_PACKED { NvmeBar ctrl; struct { uint32_t sq_tail; uint32_t cq_head; } doorbells[]; -} NVMeRegs; +} QEMU_ALIGNED(4 * KiB) NVMeRegs; + +QEMU_BUILD_BUG_ON(offsetof(NVMeRegs, doorbells[1]) !=3D 4096 + 8); =20 #define INDEX_ADMIN 0 #define INDEX_IO(n) (1 + n) --=20 2.26.2