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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x16sm20834041wrq.62.2020.09.14.07.07.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:07:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xTKrYdJw5W5WcdOTEayEo1utbID49gqxZV+lv2iSrAo=; b=b/GPUdEwpqKpVtEtXutVVr94uq5YKSGcBasVKi/O3Z9eRls+7Jqzw1iNhVNbmDPF46 dOtmdsLSDI/oWqS0uJzzY7gtqluWIZyI15qm25vdjvd09L/RIPBLDYsVJwn3rjQ0Gran 3Wg3fV/IcYCu3vR0BwvpyiFl+o2ZiMBzBbh3ZuMA8ygDjvT8hfeiU9ntwZYCpJWnfFsR ofmu42qFWwsvDQTlxZDroEW6rJyoKUk7ETIH6ht0opzWTIPi5YEXIsztb0hYpsgNJy6P mh/YW9TZ6D7rXWHq9+vzi8m5SmNektHl5sCg7lRUDgkMvEeVSo3rF954W9xwCobD2DiS 6lBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xTKrYdJw5W5WcdOTEayEo1utbID49gqxZV+lv2iSrAo=; b=NyGN39X8/+ylpL9ZnbayR4SNkxQ1QTxCDDp9NiqMwXU5BEri8QC2DxYAL04rgj3W4C Ut54p10ysZ24n/iM/MINutV8exLAaR5RU/t/drtxS2ZoE084Fw5oE7iz0+qRelcwxBrw B9dfR9g5tdk3+3C1cvE+RrNcoosID1/4qRO00p7kUg8fAsEgC0maLr/CdHatoMiYi4oe guIf1IyoKcNksfjoP18a9Z/C0kZfyh0TM9aNkiCZHb0AUwfLKM5S7KvTrKdJgTlakgBc NveJSuHMzWDjr09ZjACAK4btEN1gzvB/8RXquAAYc8ZIae3xVbgjMS1wTcDt67gI7HY3 t1OA== X-Gm-Message-State: AOAM531HJGt2CpKjqf8Bx3DHncGVzBTwlUMiWLnIl+ROaXiEoF/Frf1T EYoZlxRTxZGqwizwecVUpG4TdMH6zLLKjVRG X-Google-Smtp-Source: ABdhPJzCqcipjDb8F1m0H8hkK4LvSC55JHRcsmFbhXgrHvIQcSAMzdfPubG7aidU8VgxdpCxTHr/zQ== X-Received: by 2002:a7b:c1d4:: with SMTP id a20mr15296345wmj.30.1600092429626; Mon, 14 Sep 2020 07:07:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/36] hw/arm: Add two NPCM7xx-based machines Date: Mon, 14 Sep 2020 15:06:28 +0100 Message-Id: <20200914140641.21369-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200914140641.21369-1-peter.maydell@linaro.org> References: <20200914140641.21369-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Havard Skinnemoen This adds two new machines, both supported by OpenBMC: - npcm750-evb: Nuvoton NPCM750 Evaluation Board. - quanta-gsj: A board with a NPCM730 chip. They rely on the NPCM7xx SoC device to do the heavy lifting. They are almost completely identical at the moment, apart from the SoC type, which currently only changes the reset contents of one register (GCR.MDLR), but they might grow apart a bit more as more functionality is added. Both machines can boot the Linux kernel into /bin/sh. Reviewed-by: Tyrone Ting Reviewed-by: Joel Stanley Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Alexander Bulekov Signed-off-by: Havard Skinnemoen Message-id: 20200911052101.2602693-6-hskinnemoen@google.com Signed-off-by: Peter Maydell --- default-configs/arm-softmmu.mak | 1 + include/hw/arm/npcm7xx.h | 19 +++++ hw/arm/npcm7xx_boards.c | 145 ++++++++++++++++++++++++++++++++ hw/arm/meson.build | 2 +- 4 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 hw/arm/npcm7xx_boards.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 8fc09a4a510..9a94ebd0bef 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -27,6 +27,7 @@ CONFIG_GUMSTIX=3Dy CONFIG_SPITZ=3Dy CONFIG_TOSA=3Dy CONFIG_Z2=3Dy +CONFIG_NPCM7XX=3Dy CONFIG_COLLIE=3Dy CONFIG_ASPEED_SOC=3Dy CONFIG_NETDUINO2=3Dy diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h index e68d9c79e65..ba7495869d0 100644 --- a/include/hw/arm/npcm7xx.h +++ b/include/hw/arm/npcm7xx.h @@ -35,6 +35,25 @@ #define NPCM7XX_SMP_BOOTREG_ADDR (0xf080013c) /* GCR.SCRPAD */ #define NPCM7XX_GIC_CPU_IF_ADDR (0xf03fe100) /* GIC within A9 */ =20 +typedef struct NPCM7xxMachine { + MachineState parent; +} NPCM7xxMachine; + +#define TYPE_NPCM7XX_MACHINE MACHINE_TYPE_NAME("npcm7xx") +#define NPCM7XX_MACHINE(obj) \ + OBJECT_CHECK(NPCM7xxMachine, (obj), TYPE_NPCM7XX_MACHINE) + +typedef struct NPCM7xxMachineClass { + MachineClass parent; + + const char *soc_type; +} NPCM7xxMachineClass; + +#define NPCM7XX_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(NPCM7xxMachineClass, (klass), TYPE_NPCM7XX_MACHINE) +#define NPCM7XX_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(NPCM7xxMachineClass, (obj), TYPE_NPCM7XX_MACHINE) + typedef struct NPCM7xxState { DeviceState parent; =20 diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c new file mode 100644 index 00000000000..939391c3a3c --- /dev/null +++ b/hw/arm/npcm7xx_boards.c @@ -0,0 +1,145 @@ +/* + * Machine definitions for boards featuring an NPCM7xx SoC. + * + * Copyright 2020 Google LLC + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WIT= HOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + */ + +#include "qemu/osdep.h" + +#include "exec/address-spaces.h" +#include "hw/arm/npcm7xx.h" +#include "hw/core/cpu.h" +#include "qapi/error.h" +#include "qemu/units.h" + +#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 +#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff + +static void npcm7xx_connect_dram(NPCM7xxState *soc, MemoryRegion *dram) +{ + memory_region_add_subregion(get_system_memory(), NPCM7XX_DRAM_BA, dram= ); + + object_property_set_link(OBJECT(soc), "dram-mr", OBJECT(dram), + &error_abort); +} + +static NPCM7xxState *npcm7xx_create_soc(MachineState *machine, + uint32_t hw_straps) +{ + NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_GET_CLASS(machine); + MachineClass *mc =3D &nmc->parent; + Object *obj; + + if (strcmp(machine->cpu_type, mc->default_cpu_type) !=3D 0) { + error_report("This board can only be used with %s", + mc->default_cpu_type); + exit(1); + } + + obj =3D object_new_with_props(nmc->soc_type, OBJECT(machine), "soc", + &error_abort, NULL); + object_property_set_uint(obj, "power-on-straps", hw_straps, &error_abo= rt); + + return NPCM7XX(obj); +} + +static void npcm750_evb_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc =3D npcm7xx_create_soc(machine, NPCM750_EVB_POWER_ON_STRAPS); + npcm7xx_connect_dram(soc, machine->ram); + qdev_realize(DEVICE(soc), NULL, &error_fatal); + + npcm7xx_load_kernel(machine, soc); +} + +static void quanta_gsj_init(MachineState *machine) +{ + NPCM7xxState *soc; + + soc =3D npcm7xx_create_soc(machine, QUANTA_GSJ_POWER_ON_STRAPS); + npcm7xx_connect_dram(soc, machine->ram); + qdev_realize(DEVICE(soc), NULL, &error_fatal); + + npcm7xx_load_kernel(machine, soc); +} + +static void npcm7xx_set_soc_type(NPCM7xxMachineClass *nmc, const char *typ= e) +{ + NPCM7xxClass *sc =3D NPCM7XX_CLASS(object_class_by_name(type)); + MachineClass *mc =3D MACHINE_CLASS(nmc); + + nmc->soc_type =3D type; + mc->default_cpus =3D mc->min_cpus =3D mc->max_cpus =3D sc->num_cpus; +} + +static void npcm7xx_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->no_floppy =3D 1; + mc->no_cdrom =3D 1; + mc->no_parallel =3D 1; + mc->default_ram_id =3D "ram"; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a9"); +} + +/* + * Schematics: + * https://github.com/Nuvoton-Israel/nuvoton-info/blob/master/npcm7xx-pole= g/evaluation-board/board_deliverables/NPCM750x_EB_ver.A1.1_COMPLETE.pdf + */ +static void npcm750_evb_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM750); + + mc->desc =3D "Nuvoton NPCM750 Evaluation Board (Cortex A9)"; + mc->init =3D npcm750_evb_init; + mc->default_ram_size =3D 512 * MiB; +}; + +static void gsj_machine_class_init(ObjectClass *oc, void *data) +{ + NPCM7xxMachineClass *nmc =3D NPCM7XX_MACHINE_CLASS(oc); + MachineClass *mc =3D MACHINE_CLASS(oc); + + npcm7xx_set_soc_type(nmc, TYPE_NPCM730); + + mc->desc =3D "Quanta GSJ (Cortex A9)"; + mc->init =3D quanta_gsj_init; + mc->default_ram_size =3D 512 * MiB; +}; + +static const TypeInfo npcm7xx_machine_types[] =3D { + { + .name =3D TYPE_NPCM7XX_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(NPCM7xxMachine), + .class_size =3D sizeof(NPCM7xxMachineClass), + .class_init =3D npcm7xx_machine_class_init, + .abstract =3D true, + }, { + .name =3D MACHINE_TYPE_NAME("npcm750-evb"), + .parent =3D TYPE_NPCM7XX_MACHINE, + .class_init =3D npcm750_evb_machine_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("quanta-gsj"), + .parent =3D TYPE_NPCM7XX_MACHINE, + .class_init =3D gsj_machine_class_init, + }, +}; + +DEFINE_TYPES(npcm7xx_machine_types) diff --git a/hw/arm/meson.build b/hw/arm/meson.build index b0967c44c95..be39117b9b6 100644 --- a/hw/arm/meson.build +++ b/hw/arm/meson.build @@ -13,7 +13,7 @@ arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('micro= bit.c')) arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) arm_ss.add(when: 'CONFIG_NETDUINO2', if_true: files('netduino2.c')) arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) -arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c')) +arm_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx.c', 'npcm7xx_bo= ards.c')) arm_ss.add(when: 'CONFIG_NSERIES', if_true: files('nseries.c')) arm_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c')) arm_ss.add(when: 'CONFIG_CHEETAH', if_true: files('palm.c')) --=20 2.20.1