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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x16sm20834041wrq.62.2020.09.14.07.06.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=M14ia7zdqe++jgIV5QiQr6O0hwvccgqXO2nUDra5AE4=; b=X5AqPFbkurODq9K1A0Ff/U84UFpENYFQmNPJJXcnQ/1ZBcU/4jqExthx/HalDbQ9o7 GdcfcyA0S6yRmh9nmEc4Fuu1S1zy61mGYEdSggi5v8TGXSsAfAcWpJ0//J++oAu0G9uP P5zrdkGewnG0xB3bfgxe4wwBNOMY4U52yOzTtsmAfBqWwg46ESEv4UAanNqrJHiNh4k9 3a4+TPOmgVyFy65/uZHRA5rZ/7lKjnqvdLRI5VoEZRAzkzJYsTMf48u46CMx7MFsa/Ku 2kDaf2iqHcGXo31zwXeSq29sj1z+VR12x5fVwCiAApR5cytG07w5cfIKu56nc7PCjIG+ Vp5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M14ia7zdqe++jgIV5QiQr6O0hwvccgqXO2nUDra5AE4=; b=fpfaC3KrXbq8fOO5Y+tSoD4yJ9+n1UR43MLJWGEiHkhxzOCePaImGrzvzyoFWu5G5l jo31c5sdw7lyVlxAWSMrzoY0i1A/FurX2g+w7NB+k0jvf0kbKfUuT8FGmzvCKu1IO32W lKBe20K/fbB+G/voQuP7tvRNz/Av9XyfBQ6f6PfipVmVJ4+IlN/hCzWiAITCYxpIglCT ph4x6m9OeTtqp5o30Jf1r6GiVLS+fA/1R0lXGYCMc8u7P3e06xeFfdi89dIV0YqJGylv UVGOKbpuzN8JV+gpMGuoSf5UbIgTIkMxYM+Fdb/17XUYS5FeudNMCCG8Lx2k4S6QKhr4 v5Kw== X-Gm-Message-State: AOAM531OHHPrIi2GPWLbHg129tB5mRpU0v1uEN5YvsNvXaeOEdY/clnd zWp7Q/U0g+fKgspnQfuqX87FYLR+9XwFCTcH X-Google-Smtp-Source: ABdhPJxaTjcu9AfAEkpl0on9wUCPuq1GOgn83/boenpFCaOWNF+8xsxoXmV+ovn+MwpDrryN2YKclg== X-Received: by 2002:adf:9027:: with SMTP id h36mr15904658wrh.259.1600092419401; Mon, 14 Sep 2020 07:06:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/36] docs/system/arm/mps2.rst: Make board list consistent Date: Mon, 14 Sep 2020 15:06:19 +0100 Message-Id: <20200914140641.21369-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200914140641.21369-1-peter.maydell@linaro.org> References: <20200914140641.21369-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42e.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Make the list of MPS2 boards consistent in the phrasing of each entry, use the correct casing of "Arm", and move the mps2-an511 entry so the list is in numeric order. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200903202048.15370-4-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 7f2e9c8d52e..8c5b5f1fe07 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -11,17 +11,17 @@ as seen by the guest depend significantly on the FPGA i= mage. QEMU models the following FPGA images: =20 ``mps2-an385`` - Cortex-M3 as documented in ARM Application Note AN385 + Cortex-M3 as documented in Arm Application Note AN385 ``mps2-an386`` - Cortex-M4 as documented in ARM Application Note AN386 + Cortex-M4 as documented in Arm Application Note AN386 ``mps2-an500`` - Cortex-M7 as documented in ARM Application Note AN500 -``mps2-an511`` - Cortex-M3 'DesignStart' as documented in AN511 + Cortex-M7 as documented in Arm Application Note AN500 ``mps2-an505`` - Cortex-M33 as documented in ARM Application Note AN505 + Cortex-M33 as documented in Arm Application Note AN505 +``mps2-an511`` + Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` - Dual Cortex-M33 as documented in Application Note AN521 + Dual Cortex-M33 as documented in Arm Application Note AN521 =20 Differences between QEMU and real hardware: =20 --=20 2.20.1