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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x16sm20834041wrq.62.2020.09.14.07.06.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W46vdnAOZWxYuiCOcRluwg5RunZBfavA1+5v0cgkd8k=; b=l9VS+KrDtbBFwVyTyKaomilMXVW5y3sqmTWHac3QZMlEcjrDGEeRfeA6r+HAZGOYs1 oa2g3DdbxOOmFz/+yvbF0pWlv1PWzN4uihKl8Renel65JXYD0aQwHMe4swVbhNb6zrGn jnfqvO7tGlgZSgVI+3nbJEgRNj42lkwim++CL0nsptBRSXXDiRkOG1tkB6iqQz4P9IGK PCaS4wOHu4pzQON95kXwPQEgl6ZlstDv9Y0t415182qOhrYaqQy0LJbLqtDkTYhtJZ3w Oe4f0wZoybmoDov7G+SgfbB8LeMgEhU0ACyyYHtKVfEt8+fCgIFgAPi9HphIvTb5J4Ag cVrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W46vdnAOZWxYuiCOcRluwg5RunZBfavA1+5v0cgkd8k=; b=CsCd1VaSr2/fs1vyncpAnNHAhjBRRbV7vgQ3U5vlcBOcC3L01Xx31DLEXTyQ0j5L6D pbZfmEGYBT57mHudA0mo3nngs6lUMe46/9cPSrUAYI5XPvt6+GcPgcSnmvGHBChvVJM5 YHsf4vPvjXtWns1hprFX3NszdxN3o7DrtcDWPt0RKeVtrDrg2Lr/olYqxVa63Jv+zDFR 6PBoFBRtTDxmHC7v7T133CfMmLoWlj05k9cS9lzdOk4N6d7SRIHX3P0j+/kLYRlq78t+ eEbnYPfQdtDQlmkimK6ILdwRKDel7T+qmd+tGf0hkbZVeGfkU2Rt+D/lMmPKKB/+gdnV cGgA== X-Gm-Message-State: AOAM531rghfpHxRdOwboAhhveooC7w0uOf9FflQIsx4HssFbZk6hn9Of RlutbANbuIKBAkDvH0dDD+d+jiIB48EnUTqv X-Google-Smtp-Source: ABdhPJwH8lBO62oS4DVRJXfyaoRsssMcmIpKDShmCIds5XT2qdWflBnldQDmsAW/tb69ae2dP0Y2BQ== X-Received: by 2002:adf:efc9:: with SMTP id i9mr16806263wrp.187.1600092417141; Mon, 14 Sep 2020 07:06:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/36] hw/arm/mps2: New board model mps2-an386 Date: Mon, 14 Sep 2020 15:06:17 +0100 Message-Id: <20200914140641.21369-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200914140641.21369-1-peter.maydell@linaro.org> References: <20200914140641.21369-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200903202048.15370-2-peter.maydell@linaro.org --- docs/system/arm/mps2.rst | 8 +++++--- hw/arm/mps2.c | 34 +++++++++++++++++++++++++++++----- 2 files changed, 34 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 3a98cb59b0d..e680a4ceb71 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an= 521``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an= 511``, ``mps2-an521``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models all use Arm M-profile CPUs. =20 @@ -12,6 +12,8 @@ QEMU models the following FPGA images: =20 ``mps2-an385`` Cortex-M3 as documented in ARM Application Note AN385 +``mps2-an386`` + Cortex-M4 as documented in ARM Application Note AN386 ``mps2-an511`` Cortex-M3 'DesignStart' as documented in AN511 ``mps2-an505`` @@ -21,7 +23,7 @@ QEMU models the following FPGA images: =20 Differences between QEMU and real hardware: =20 -- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to +- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 4ee5c38459e..d3ec73fbe78 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -15,6 +15,7 @@ * as seen by the guest depend significantly on the FPGA image. * We model the following FPGA images: * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 + * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 * * Links to the TRM for the board itself and to the various Application @@ -48,6 +49,7 @@ =20 typedef enum MPS2FPGAType { FPGA_AN385, + FPGA_AN386, FPGA_AN511, } MPS2FPGAType; =20 @@ -82,6 +84,7 @@ typedef struct MPS2MachineState MPS2MachineState; =20 #define TYPE_MPS2_MACHINE "mps2" #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") +#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386") #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") =20 DECLARE_OBJ_CHECKERS(MPS2MachineState, MPS2MachineClass, @@ -139,9 +142,9 @@ static void mps2_common_init(MachineState *machine) * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily * call the 16MB our "system memory", as it's the largest lump. * - * Common to both boards: - * 0x21000000..0x21ffffff : PSRAM (16MB) - * AN385 only: + * AN385/AN386/AN511: + * 0x21000000 .. 0x21ffffff : PSRAM (16MB) + * AN385/AN386 only: * 0x00000000 .. 0x003fffff : ZBT SSRAM1 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 @@ -156,7 +159,7 @@ static void mps2_common_init(MachineState *machine) * 0x20000000 .. 0x2001ffff : SRAM * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 * - * The AN385 has a feature where the lowest 16K can be mapped + * The AN385/AN386 has a feature where the lowest 16K can be mapped * either to the bottom of the ZBT SSRAM1 or to the block RAM. * This is of no use for QEMU so we don't implement it (as if * zbt_boot_ctrl is always zero). @@ -165,6 +168,7 @@ static void mps2_common_init(MachineState *machine) =20 switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400= 000); make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); @@ -192,6 +196,7 @@ static void mps2_common_init(MachineState *machine) armv7m =3D DEVICE(&mms->armv7m); switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: @@ -228,6 +233,7 @@ static void mps2_common_init(MachineState *machine) =20 switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: { /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. @@ -379,7 +385,7 @@ static void mps2_common_init(MachineState *machine) */ lan9118_init(&nd_table[0], 0x40200000, qdev_get_gpio_in(armv7m, - mmc->fpga_type =3D=3D FPGA_AN385 ? 13 : = 47)); + mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 @@ -408,6 +414,17 @@ static void mps2_an385_class_init(ObjectClass *oc, voi= d *data) mmc->scc_id =3D 0x41043850; } =20 +static void mps2_an386_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS2 with AN386 FPGA image for Cortex-M4"; + mmc->fpga_type =3D FPGA_AN386; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + mmc->scc_id =3D 0x41043860; +} + static void mps2_an511_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -434,6 +451,12 @@ static const TypeInfo mps2_an385_info =3D { .class_init =3D mps2_an385_class_init, }; =20 +static const TypeInfo mps2_an386_info =3D { + .name =3D TYPE_MPS2_AN386_MACHINE, + .parent =3D TYPE_MPS2_MACHINE, + .class_init =3D mps2_an386_class_init, +}; + static const TypeInfo mps2_an511_info =3D { .name =3D TYPE_MPS2_AN511_MACHINE, .parent =3D TYPE_MPS2_MACHINE, @@ -444,6 +467,7 @@ static void mps2_machine_init(void) { type_register_static(&mps2_info); type_register_static(&mps2_an385_info); + type_register_static(&mps2_an386_info); type_register_static(&mps2_an511_info); } =20 --=20 2.20.1