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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id x16sm20834041wrq.62.2020.09.14.07.06.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Sep 2020 07:06:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2Pm0HMO2zXGIGpZaPm/owGvMJz02qx44BSYos4Dfokk=; b=t+NO/wXWg95yON2MqwdHg0QRP2HibN1G+cwm9+XGZnQbkFJH3Lyms6IUaBAKLpyGyF Otx5t7lU8LimIHpaooSVRHpDeQbEI5ePcRqBabXjWfOdT0O7RVXAN//5/txvGIkvWNVR nG9i87/MkaldM4FIw9fhkSne5z9784IgsifLbRGzLgFFmJPmomEZMGzzmLIbUazK3BT/ pQUyAuvlXilswqNUqIlQVz2j1VTpvc2yOi5T4UfN4kWgJvIwOOXMrtGSflT3zqUxygkW gWkbdgfab8t6M/hKNXGLTGIYtVRRtiHraADk6p2MLkYvDcdg+iLgUaqaSt+u3EvjIWxZ VJQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2Pm0HMO2zXGIGpZaPm/owGvMJz02qx44BSYos4Dfokk=; b=pUWsUJkuB3i0bjICc6Qu+qSOUxT7QZvVsfpJsdsEewgaRqoYjFNRy3WCijcca6fe7X crfIJffhGeuAm6WPtwpKYqJQuE8t+HETLH9Wf4rFOqDfnLONxa77HR1nPwim0rRbUQBb sBXPGC59tTBHuFtcxlcEY09fZGd9TAzLO9SrKHBZoU5nX613SFGmsrYyWrMX7bV1sJ/T UFC1bg+nrilg6mwqMTkIncBdsljhRujY7LlGg7i74jZG81ne9jMXiIDT0ZMWOBk9uL9Q edXJ9yUspJSQ4kWg3RHmQR3x3e/V5ljgbH1Z/XWgprnn2RQ6KfpirSErz0K01/pRS4Xx 6cWQ== X-Gm-Message-State: AOAM531E7w03WElsD6OJxH+Q+RqM/K06XWqwU0Fqb3vw/PwmIs0+2Au+ BqBNfYs8K5Zcl9AlBYem/TDu+FpMfdTtF+GU X-Google-Smtp-Source: ABdhPJwuJx/ruZ1revnFG+IIRHwyn4qSpBXabThyyhbemPMUBL7sXgYNKVLy9hQJhKev0OvQhA3x8w== X-Received: by 2002:a7b:c241:: with SMTP id b1mr15154416wmj.98.1600092415593; Mon, 14 Sep 2020 07:06:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/36] target/arm: Remove no-longer-reachable 32-bit KVM code Date: Mon, 14 Sep 2020 15:06:16 +0100 Message-Id: <20200914140641.21369-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200914140641.21369-1-peter.maydell@linaro.org> References: <20200914140641.21369-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Now that 32-bit KVM host support is gone, KVM can never be enabled unless CONFIG_AARCH64 is true, and some code paths are no longer reachable and can be deleted. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200904154156.31943-3-peter.maydell@linaro.org --- target/arm/kvm-consts.h | 7 --- target/arm/kvm_arm.h | 6 --- target/arm/cpu.c | 101 +++++++++++++++++++--------------------- target/arm/kvm.c | 7 --- 4 files changed, 47 insertions(+), 74 deletions(-) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index aad28258a36..580f1c1fee0 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -136,16 +136,11 @@ MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISAB= LED); */ #define QEMU_KVM_ARM_TARGET_NONE UINT_MAX =20 -#ifdef TARGET_AARCH64 MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_AEM_V8, KVM_ARM_TARGET_AEM_V8); MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_FOUNDATION_V8, KVM_ARM_TARGET_FOUNDATIO= N_V8); MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A57, KVM_ARM_TARGET_CORTEX_A57); MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_XGENE_POTENZA, KVM_ARM_TARGET_XGENE_POT= ENZA); MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A53, KVM_ARM_TARGET_CORTEX_A53); -#else -MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A15, KVM_ARM_TARGET_CORTEX_A15); -MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_TARGET_CORTEX_A7); -#endif =20 #define CP_REG_ARM64 0x6000000000000000ULL #define CP_REG_ARM_COPROC_MASK 0x000000000FFF0000 @@ -165,7 +160,6 @@ MISMATCH_CHECK(QEMU_KVM_ARM_TARGET_CORTEX_A7, KVM_ARM_T= ARGET_CORTEX_A7); /* No kernel define but it's useful to QEMU */ #define CP_REG_ARM64_SYSREG_CP (CP_REG_ARM64_SYSREG >> CP_REG_ARM_COPROC_S= HIFT) =20 -#ifdef TARGET_AARCH64 MISMATCH_CHECK(CP_REG_ARM64, KVM_REG_ARM64); MISMATCH_CHECK(CP_REG_ARM_COPROC_MASK, KVM_REG_ARM_COPROC_MASK); MISMATCH_CHECK(CP_REG_ARM_COPROC_SHIFT, KVM_REG_ARM_COPROC_SHIFT); @@ -180,7 +174,6 @@ MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_MASK, KVM_REG_AR= M64_SYSREG_CRM_MASK); MISMATCH_CHECK(CP_REG_ARM64_SYSREG_CRM_SHIFT, KVM_REG_ARM64_SYSREG_CRM_SHI= FT); MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_MASK, KVM_REG_ARM64_SYSREG_OP2_MASK= ); MISMATCH_CHECK(CP_REG_ARM64_SYSREG_OP2_SHIFT, KVM_REG_ARM64_SYSREG_OP2_SHI= FT); -#endif =20 #undef MISMATCH_CHECK =20 diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index adb38514bf2..bc178eeb84c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -406,13 +406,7 @@ static inline const char *gic_class_name(void) static inline const char *gicv3_class_name(void) { if (kvm_irqchip_in_kernel()) { -#ifdef TARGET_AARCH64 return "kvm-arm-gicv3"; -#else - error_report("KVM GICv3 acceleration is not supported on this " - "platform"); - exit(1); -#endif } else { if (kvm_enabled()) { error_report("Userspace GICv3 is not supported with KVM"); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6b4e708c08f..7b5ea65fab9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2098,72 +2098,69 @@ static void cortex_a15_initfn(Object *obj) } =20 #ifndef TARGET_AARCH64 -/* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); - * otherwise, a CPU with as many features enabled as our emulation support= s. +/* + * -cpu max: a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c; - * this only needs to handle 32 bits. + * this only needs to handle 32 bits, and need not care about KVM. */ static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 - if (kvm_enabled()) { - kvm_arm_set_cpu_features_from_host(cpu); - } else { - cortex_a15_initfn(obj); + cortex_a15_initfn(obj); =20 - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + /* old-style VFP short-vector support */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); =20 #ifdef CONFIG_USER_ONLY - /* We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; + /* + * We don't set these in system emulation mode for the moment, + * since we don't correctly set (all of) the ID registers to + * advertise them. + */ + set_feature(&cpu->env, ARM_FEATURE_V8); + { + uint32_t t; =20 - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; =20 - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - cpu->isar.id_isar6 =3D t; + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + cpu->isar.id_isar6 =3D t; =20 - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; =20 - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; =20 - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - } -#endif + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; } +#endif } #endif =20 @@ -2267,11 +2264,7 @@ static void arm_host_initfn(Object *obj) =20 static const TypeInfo host_arm_cpu_type_info =3D { .name =3D TYPE_ARM_HOST_CPU, -#ifdef TARGET_AARCH64 .parent =3D TYPE_AARCH64_CPU, -#else - .parent =3D TYPE_ARM_CPU, -#endif .instance_init =3D arm_host_initfn, }; =20 diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 8bb7318378b..2eae73315d6 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -918,22 +918,15 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } =20 -/* The #ifdef protections are until 32bit headers are imported and can - * be removed once both 32 and 64 bit reach feature parity. - */ void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) { -#ifdef KVM_GUESTDBG_USE_SW_BP if (kvm_sw_breakpoints_active(cs)) { dbg->control |=3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP; } -#endif -#ifdef KVM_GUESTDBG_USE_HW if (kvm_arm_hw_debug_active(cs)) { dbg->control |=3D KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW; kvm_arm_copy_hw_debug_data(&dbg->arch); } -#endif } =20 void kvm_arch_init_irq_routing(KVMState *s) --=20 2.20.1