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charset="utf-8" From: Niklas Cassel Define the structures and constants required to implement Namespace Types support. Signed-off-by: Niklas Cassel Signed-off-by: Dmitry Fomichev --- hw/block/nvme.c | 2 +- hw/block/nvme.h | 3 ++ include/block/nvme.h | 74 +++++++++++++++++++++++++++++++++++--------- 3 files changed, 64 insertions(+), 15 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 39c2d5b0b4..4bd88f4046 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1259,7 +1259,7 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl = *n, NvmeRequest *req) * here. */ ns_descrs->uuid.hdr.nidt =3D NVME_NIDT_UUID; - ns_descrs->uuid.hdr.nidl =3D NVME_NIDT_UUID_LEN; + ns_descrs->uuid.hdr.nidl =3D NVME_NIDL_UUID; stl_be_p(&ns_descrs->uuid.v, nsid); =20 return nvme_dma_prp(n, list, NVME_IDENTIFY_DATA_SIZE, prp1, prp2, diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 190c974b6c..252e2d5921 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -64,6 +64,9 @@ typedef struct NvmeCQueue { =20 typedef struct NvmeNamespace { NvmeIdNs id_ns; + uint32_t nsid; + uint8_t csi; + QemuUUID uuid; } NvmeNamespace; =20 static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) diff --git a/include/block/nvme.h b/include/block/nvme.h index 62136a906f..f2cff5aa6b 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -51,6 +51,11 @@ enum NvmeCapMask { CAP_PMR_MASK =3D 0x1, }; =20 +enum NvmeCapCssBits { + CAP_CSS_NVM =3D 0x01, + CAP_CSS_CSI_SUPP =3D 0x40, +}; + #define NVME_CAP_MQES(cap) (((cap) >> CAP_MQES_SHIFT) & CAP_MQES_MASK) #define NVME_CAP_CQR(cap) (((cap) >> CAP_CQR_SHIFT) & CAP_CQR_MASK) #define NVME_CAP_AMS(cap) (((cap) >> CAP_AMS_SHIFT) & CAP_AMS_MASK) @@ -102,6 +107,12 @@ enum NvmeCcMask { CC_IOCQES_MASK =3D 0xf, }; =20 +enum NvmeCcCss { + CSS_NVM_ONLY =3D 0, + CSS_CSI =3D 6, + CSS_ADMIN_ONLY =3D 7, +}; + #define NVME_CC_EN(cc) ((cc >> CC_EN_SHIFT) & CC_EN_MASK) #define NVME_CC_CSS(cc) ((cc >> CC_CSS_SHIFT) & CC_CSS_MASK) #define NVME_CC_MPS(cc) ((cc >> CC_MPS_SHIFT) & CC_MPS_MASK) @@ -110,6 +121,21 @@ enum NvmeCcMask { #define NVME_CC_IOSQES(cc) ((cc >> CC_IOSQES_SHIFT) & CC_IOSQES_MASK) #define NVME_CC_IOCQES(cc) ((cc >> CC_IOCQES_SHIFT) & CC_IOCQES_MASK) =20 +#define NVME_SET_CC_EN(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_EN_MASK) << CC_EN_SHIFT) +#define NVME_SET_CC_CSS(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_CSS_MASK) << CC_CSS_SHIFT) +#define NVME_SET_CC_MPS(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_MPS_MASK) << CC_MPS_SHIFT) +#define NVME_SET_CC_AMS(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_AMS_MASK) << CC_AMS_SHIFT) +#define NVME_SET_CC_SHN(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_SHN_MASK) << CC_SHN_SHIFT) +#define NVME_SET_CC_IOSQES(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_IOSQES_MASK) << CC_IOSQES_SHIFT) +#define NVME_SET_CC_IOCQES(cc, val) \ + (cc |=3D (uint32_t)((val) & CC_IOCQES_MASK) << CC_IOCQES_SHIFT) + enum NvmeCstsShift { CSTS_RDY_SHIFT =3D 0, CSTS_CFS_SHIFT =3D 1, @@ -524,8 +550,13 @@ typedef struct QEMU_PACKED NvmeIdentify { uint64_t rsvd2[2]; uint64_t prp1; uint64_t prp2; - uint32_t cns; - uint32_t rsvd11[5]; + uint8_t cns; + uint8_t rsvd10; + uint16_t ctrlid; + uint16_t nvmsetid; + uint8_t rsvd11; + uint8_t csi; + uint32_t rsvd12[4]; } NvmeIdentify; =20 typedef struct QEMU_PACKED NvmeRwCmd { @@ -647,6 +678,7 @@ enum NvmeStatusCodes { NVME_MD_SGL_LEN_INVALID =3D 0x0010, NVME_SGL_DESCR_TYPE_INVALID =3D 0x0011, NVME_INVALID_USE_OF_CMB =3D 0x0012, + NVME_CMD_SET_CMB_REJECTED =3D 0x002b, NVME_LBA_RANGE =3D 0x0080, NVME_CAP_EXCEEDED =3D 0x0081, NVME_NS_NOT_READY =3D 0x0082, @@ -773,11 +805,15 @@ typedef struct QEMU_PACKED NvmePSD { =20 #define NVME_IDENTIFY_DATA_SIZE 4096 =20 -enum { - NVME_ID_CNS_NS =3D 0x0, - NVME_ID_CNS_CTRL =3D 0x1, - NVME_ID_CNS_NS_ACTIVE_LIST =3D 0x2, - NVME_ID_CNS_NS_DESCR_LIST =3D 0x3, +enum NvmeIdCns { + NVME_ID_CNS_NS =3D 0x00, + NVME_ID_CNS_CTRL =3D 0x01, + NVME_ID_CNS_NS_ACTIVE_LIST =3D 0x02, + NVME_ID_CNS_NS_DESCR_LIST =3D 0x03, + NVME_ID_CNS_CS_NS =3D 0x05, + NVME_ID_CNS_CS_CTRL =3D 0x06, + NVME_ID_CNS_CS_NS_ACTIVE_LIST =3D 0x07, + NVME_ID_CNS_IO_COMMAND_SET =3D 0x1c, }; =20 typedef struct QEMU_PACKED NvmeIdCtrl { @@ -924,6 +960,7 @@ enum NvmeFeatureIds { NVME_WRITE_ATOMICITY =3D 0xa, NVME_ASYNCHRONOUS_EVENT_CONF =3D 0xb, NVME_TIMESTAMP =3D 0xe, + NVME_COMMAND_SET_PROFILE =3D 0x19, NVME_SOFTWARE_PROGRESS_MARKER =3D 0x80, NVME_FID_MAX =3D 0x100, }; @@ -1008,18 +1045,26 @@ typedef struct QEMU_PACKED NvmeIdNsDescr { uint8_t rsvd2[2]; } NvmeIdNsDescr; =20 -enum { - NVME_NIDT_EUI64_LEN =3D 8, - NVME_NIDT_NGUID_LEN =3D 16, - NVME_NIDT_UUID_LEN =3D 16, +enum NvmeNsIdentifierLength { + NVME_NIDL_EUI64 =3D 8, + NVME_NIDL_NGUID =3D 16, + NVME_NIDL_UUID =3D 16, + NVME_NIDL_CSI =3D 1, }; =20 enum NvmeNsIdentifierType { - NVME_NIDT_EUI64 =3D 0x1, - NVME_NIDT_NGUID =3D 0x2, - NVME_NIDT_UUID =3D 0x3, + NVME_NIDT_EUI64 =3D 0x01, + NVME_NIDT_NGUID =3D 0x02, + NVME_NIDT_UUID =3D 0x03, + NVME_NIDT_CSI =3D 0x04, }; =20 +enum NvmeCsi { + NVME_CSI_NVM =3D 0x00, +}; + +#define NVME_SET_CSI(vec, csi) (vec |=3D (uint8_t)(1 << (csi))) + /*Deallocate Logical Block Features*/ #define NVME_ID_NS_DLFEAT_GUARD_CRC(dlfeat) ((dlfeat) & 0x10) #define NVME_ID_NS_DLFEAT_WRITE_ZEROES(dlfeat) ((dlfeat) & 0x08) @@ -1070,6 +1115,7 @@ static inline void _nvme_check_size(void) QEMU_BUILD_BUG_ON(sizeof(NvmeSmartLog) !=3D 512); QEMU_BUILD_BUG_ON(sizeof(NvmeEffectsLog) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeIdCtrl) !=3D 4096); + QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) !=3D 4); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNs) !=3D 4096); QEMU_BUILD_BUG_ON(sizeof(NvmeSglDescriptor) !=3D 16); QEMU_BUILD_BUG_ON(sizeof(NvmeIdNsDescr) !=3D 4); --=20 2.21.0