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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=517336518=dmitry.fomichev@wdc.com; helo=esa1.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/12 18:54:38 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Niklas Cassel , Damien Le Moal , qemu-block@nongnu.org, Dmitry Fomichev , qemu-devel@nongnu.org, Alistair Francis , Matias Bjorling Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The Zoned Namespace Command Set / Namespace Types implementation that is being introduced in this series adds a good number of trace events. Combine all tracepoint definitions into a separate patch to make reviewing more convenient. Signed-off-by: Dmitry Fomichev --- hw/block/trace-events | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/hw/block/trace-events b/hw/block/trace-events index 2414dcbc79..53c7a2fd1f 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -90,6 +90,17 @@ pci_nvme_mmio_shutdown_cleared(void) "shutdown bit clear= ed" pci_nvme_cmd_supp_and_effects_log_read(void) "commands supported and effec= ts log read" pci_nvme_css_nvm_cset_selected_by_host(uint32_t cc) "NVM command set selec= ted by host, bar.cc=3D0x%"PRIx32"" pci_nvme_css_all_csets_sel_by_host(uint32_t cc) "all supported command set= s selected by host, bar.cc=3D0x%"PRIx32"" +pci_nvme_open_zone(uint64_t slba, uint32_t zone_idx, int all) "open zone, = slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_close_zone(uint64_t slba, uint32_t zone_idx, int all) "close zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_finish_zone(uint64_t slba, uint32_t zone_idx, int all) "finish zo= ne, slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_reset_zone(uint64_t slba, uint32_t zone_idx, int all) "reset zone= , slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_offline_zone(uint64_t slba, uint32_t zone_idx, int all) "offline = zone, slba=3D%"PRIu64", idx=3D%"PRIu32", all=3D%"PRIi32"" +pci_nvme_set_descriptor_extension(uint64_t slba, uint32_t zone_idx) "set z= one descriptor extension, slba=3D%"PRIu64", idx=3D%"PRIu32"" +pci_nvme_zd_extension_set(uint32_t zone_idx) "set descriptor extension for= zone_idx=3D%"PRIu32"" +pci_nvme_power_on_close(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Closed state" +pci_nvme_power_on_reset(uint32_t state, uint64_t slba) "zone state=3D%"PRI= u32", slba=3D%"PRIu64" transitioned to Empty state" +pci_nvme_power_on_full(uint32_t state, uint64_t slba) "zone state=3D%"PRIu= 32", slba=3D%"PRIu64" transitioned to Full state" +pci_nvme_mapped_zone_file(char *zfile_name, int ret) "mapped zone file %s,= error %d" =20 # nvme traces for error conditions pci_nvme_err_mdts(uint16_t cid, size_t len) "cid %"PRIu16" len %zu" @@ -102,9 +113,23 @@ pci_nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "= invalid namespace %u not w pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_unaligned_zone_cmd(uint8_t action, uint64_t slba, uint64_t zs= lba) "unaligned zone op 0x%"PRIx32", got slba=3D%"PRIu64", zslba=3D%"PRIu64= "" +pci_nvme_err_invalid_zone_state_transition(uint8_t state, uint8_t action, = uint64_t slba, uint8_t attrs) "0x%"PRIx32"->0x%"PRIx32", slba=3D%"PRIu64", = attrs=3D0x%"PRIx32"" +pci_nvme_err_write_not_at_wp(uint64_t slba, uint64_t zone, uint64_t wp) "w= riting at slba=3D%"PRIu64", zone=3D%"PRIu64", but wp=3D%"PRIu64"" +pci_nvme_err_append_not_at_start(uint64_t slba, uint64_t zone) "appending = at slba=3D%"PRIu64", but zone=3D%"PRIu64"" +pci_nvme_err_zone_write_not_ok(uint64_t slba, uint32_t nlb, uint32_t statu= s) "slba=3D%"PRIu64", nlb=3D%"PRIu32", status=3D0x%"PRIx16"" +pci_nvme_err_zone_read_not_ok(uint64_t slba, uint32_t nlb, uint32_t status= ) "slba=3D%"PRIu64", nlb=3D%"PRIu32", status=3D0x%"PRIx16"" +pci_nvme_err_append_too_large(uint64_t slba, uint32_t nlb, uint8_t zasl) "= slba=3D%"PRIu64", nlb=3D%"PRIu32", zasl=3D%"PRIu8"" +pci_nvme_err_insuff_active_res(uint32_t max_active) "max_active=3D%"PRIu32= " zone limit exceeded" +pci_nvme_err_insuff_open_res(uint32_t max_open) "max_open=3D%"PRIu32" zone= limit exceeded" +pci_nvme_err_zone_file_invalid(int error) "validation error=3D%"PRIi32"" +pci_nvme_err_zd_extension_map_error(uint32_t zone_idx) "can't map descript= or extension for zone_idx=3D%"PRIu32"" +pci_nvme_err_invalid_changed_zone_list_offset(uint64_t ofs) "changed zone = list log offset must be 0, got %"PRIu64"" +pci_nvme_err_invalid_changed_zone_list_len(uint32_t len) "changed zone lis= t log size is 4096, got %"PRIu32"" pci_nvme_err_invalid_effects_log_offset(uint64_t ofs) "commands supported = and effects log offset must be 0, got %"PRIu64"" pci_nvme_err_change_css_when_enabled(void) "changing CC.CSS while controll= er is enabled" pci_nvme_err_only_nvm_cmd_set_avail(void) "setting 110b CC.CSS, but only N= VM command set is enabled" +pci_nvme_err_only_zoned_cmd_set_avail(void) "setting 001b CC.CSS, but only= ZONED+NVM command set is enabled" pci_nvme_err_invalid_iocsci(uint32_t idx) "unsupported command set combina= tion index %"PRIu32"" pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" @@ -138,6 +163,7 @@ pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, = uint8_t maxlog2ps) "nvme_ pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin submission queue size is zero" pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" pci_nvme_err_startfail(void) "setting controller enable bit failed" +pci_nvme_err_invalid_mgmt_action(int action) "action=3D0x%"PRIx8"" =20 # Traces for undefined behavior pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" --=20 2.21.0