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bh=J2LKDn5aJwqKCodEjW61DjnounBuuTDmGKf1hijDFcY=; b=dXnNWy0G6yZpgqsU8o/xYqOEWa8O6nnu8dXEcKe9LuH5ScBJolt+r+8QXgovqETGSvEoYU MX2piL1bTtc7K6QjR/GvDVUYSrMG6tPXlRxp2LH6Cwzj4ynpII6VnQpMMe1xtSYrgj3yyt JxTChlnyFuk5ONMDbdygpZq3RR2ZDU0= X-MC-Unique: N94jPjuOP1O1N2kdWLa0VA-1 From: Eduardo Habkost To: qemu-devel@nongnu.org Subject: [PATCH v4 1/2] sifive_e: Rename memmap enum constants Date: Fri, 11 Sep 2020 13:34:46 -0400 Message-Id: <20200911173447.165713-2-ehabkost@redhat.com> In-Reply-To: <20200911173447.165713-1-ehabkost@redhat.com> References: <20200911173447.165713-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0.001 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.205.24.124; envelope-from=ehabkost@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/10 23:26:59 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P. Berrange" , qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Some of the enum constant names conflict with a QOM type check macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost Reviewed-by: Alistair Francis --- Changes v3 -> v4: * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910 Link to v3: https://lore.kernel.org/qemu-devel/20200825192110.3528606-9-ehabkost@redhat= .com/ Changes v2 -> v3: none Changes v1 -> v2: * Added more details to commit message --- Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org --- include/hw/riscv/sifive_e.h | 38 ++++++++--------- hw/riscv/sifive_e.c | 82 ++++++++++++++++++------------------- 2 files changed, 60 insertions(+), 60 deletions(-) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index b1400843c2..83604da805 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -53,25 +53,25 @@ typedef struct SiFiveEState { OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE) =20 enum { - SIFIVE_E_DEBUG, - SIFIVE_E_MROM, - SIFIVE_E_OTP, - SIFIVE_E_CLINT, - SIFIVE_E_PLIC, - SIFIVE_E_AON, - SIFIVE_E_PRCI, - SIFIVE_E_OTP_CTRL, - SIFIVE_E_GPIO0, - SIFIVE_E_UART0, - SIFIVE_E_QSPI0, - SIFIVE_E_PWM0, - SIFIVE_E_UART1, - SIFIVE_E_QSPI1, - SIFIVE_E_PWM1, - SIFIVE_E_QSPI2, - SIFIVE_E_PWM2, - SIFIVE_E_XIP, - SIFIVE_E_DTIM + SIFIVE_E_DEV_DEBUG, + SIFIVE_E_DEV_MROM, + SIFIVE_E_DEV_OTP, + SIFIVE_E_DEV_CLINT, + SIFIVE_E_DEV_PLIC, + SIFIVE_E_DEV_AON, + SIFIVE_E_DEV_PRCI, + SIFIVE_E_DEV_OTP_CTRL, + SIFIVE_E_DEV_GPIO0, + SIFIVE_E_DEV_UART0, + SIFIVE_E_DEV_QSPI0, + SIFIVE_E_DEV_PWM0, + SIFIVE_E_DEV_UART1, + SIFIVE_E_DEV_QSPI1, + SIFIVE_E_DEV_PWM1, + SIFIVE_E_DEV_QSPI2, + SIFIVE_E_DEV_PWM2, + SIFIVE_E_DEV_XIP, + SIFIVE_E_DEV_DTIM }; =20 enum { diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 40bbf530d4..759059cd7b 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -54,25 +54,25 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_e_memmap[] =3D { - [SIFIVE_E_DEBUG] =3D { 0x0, 0x1000 }, - [SIFIVE_E_MROM] =3D { 0x1000, 0x2000 }, - [SIFIVE_E_OTP] =3D { 0x20000, 0x2000 }, - [SIFIVE_E_CLINT] =3D { 0x2000000, 0x10000 }, - [SIFIVE_E_PLIC] =3D { 0xc000000, 0x4000000 }, - [SIFIVE_E_AON] =3D { 0x10000000, 0x8000 }, - [SIFIVE_E_PRCI] =3D { 0x10008000, 0x8000 }, - [SIFIVE_E_OTP_CTRL] =3D { 0x10010000, 0x1000 }, - [SIFIVE_E_GPIO0] =3D { 0x10012000, 0x1000 }, - [SIFIVE_E_UART0] =3D { 0x10013000, 0x1000 }, - [SIFIVE_E_QSPI0] =3D { 0x10014000, 0x1000 }, - [SIFIVE_E_PWM0] =3D { 0x10015000, 0x1000 }, - [SIFIVE_E_UART1] =3D { 0x10023000, 0x1000 }, - [SIFIVE_E_QSPI1] =3D { 0x10024000, 0x1000 }, - [SIFIVE_E_PWM1] =3D { 0x10025000, 0x1000 }, - [SIFIVE_E_QSPI2] =3D { 0x10034000, 0x1000 }, - [SIFIVE_E_PWM2] =3D { 0x10035000, 0x1000 }, - [SIFIVE_E_XIP] =3D { 0x20000000, 0x20000000 }, - [SIFIVE_E_DTIM] =3D { 0x80000000, 0x4000 } + [SIFIVE_E_DEV_DEBUG] =3D { 0x0, 0x1000 }, + [SIFIVE_E_DEV_MROM] =3D { 0x1000, 0x2000 }, + [SIFIVE_E_DEV_OTP] =3D { 0x20000, 0x2000 }, + [SIFIVE_E_DEV_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_E_DEV_PLIC] =3D { 0xc000000, 0x4000000 }, + [SIFIVE_E_DEV_AON] =3D { 0x10000000, 0x8000 }, + [SIFIVE_E_DEV_PRCI] =3D { 0x10008000, 0x8000 }, + [SIFIVE_E_DEV_OTP_CTRL] =3D { 0x10010000, 0x1000 }, + [SIFIVE_E_DEV_GPIO0] =3D { 0x10012000, 0x1000 }, + [SIFIVE_E_DEV_UART0] =3D { 0x10013000, 0x1000 }, + [SIFIVE_E_DEV_QSPI0] =3D { 0x10014000, 0x1000 }, + [SIFIVE_E_DEV_PWM0] =3D { 0x10015000, 0x1000 }, + [SIFIVE_E_DEV_UART1] =3D { 0x10023000, 0x1000 }, + [SIFIVE_E_DEV_QSPI1] =3D { 0x10024000, 0x1000 }, + [SIFIVE_E_DEV_PWM1] =3D { 0x10025000, 0x1000 }, + [SIFIVE_E_DEV_QSPI2] =3D { 0x10034000, 0x1000 }, + [SIFIVE_E_DEV_PWM2] =3D { 0x10035000, 0x1000 }, + [SIFIVE_E_DEV_XIP] =3D { 0x20000000, 0x20000000 }, + [SIFIVE_E_DEV_DTIM] =3D { 0x80000000, 0x4000 } }; =20 static void sifive_e_machine_init(MachineState *machine) @@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine) =20 /* Data Tightly Integrated Memory */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", - memmap[SIFIVE_E_DTIM].size, &error_fatal); + memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_DTIM].base, main_mem); + memmap[SIFIVE_E_DEV_DTIM].base, main_mem); =20 /* Mask ROM reset vector */ uint32_t reset_vec[4]; @@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine) reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SIFIVE_E_MROM].base, &address_space_memor= y); + memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { riscv_load_kernel(machine->kernel_filename, NULL); @@ -195,12 +195,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) =20 /* Mask ROM */ memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom= ", - memmap[SIFIVE_E_MROM].size, &error_fatal); + memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_MROM].base, &s->mask_rom); + memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_E_PLIC].base, + s->plic =3D sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, (char *)SIFIVE_E_PLIC_HART_CONFIG, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, @@ -210,14 +210,14 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) SIFIVE_E_PLIC_ENABLE_STRIDE, SIFIVE_E_PLIC_CONTEXT_BASE, SIFIVE_E_PLIC_CONTEXT_STRIDE, - memmap[SIFIVE_E_PLIC].size); - sifive_clint_create(memmap[SIFIVE_E_CLINT].base, - memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, + memmap[SIFIVE_E_DEV_PLIC].size); + sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base, + memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); create_unimplemented_device("riscv.sifive.e.aon", - memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); + memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); + sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); =20 /* GPIO */ =20 @@ -226,7 +226,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* Map GPIO registers */ - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].ba= se); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0= ].base); =20 /* Pass all GPIOs to the SOC layer so they are available to the board = */ qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); @@ -238,27 +238,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) SIFIVE_E_GPIO0_IRQ0 + i)); } =20 - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ= )); create_unimplemented_device("riscv.sifive.e.qspi0", - memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); + memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); create_unimplemented_device("riscv.sifive.e.pwm0", - memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, + memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ= )); create_unimplemented_device("riscv.sifive.e.qspi1", - memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); + memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); create_unimplemented_device("riscv.sifive.e.pwm1", - memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); + memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); create_unimplemented_device("riscv.sifive.e.qspi2", - memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); + memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); create_unimplemented_device("riscv.sifive.e.pwm2", - memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); + memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); =20 /* Flash memory */ memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", - memmap[SIFIVE_E_XIP].size, &error_fatal); - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, + memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, &s->xip_mem); } =20 --=20 2.26.2