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bh=J2LKDn5aJwqKCodEjW61DjnounBuuTDmGKf1hijDFcY=; b=dXnNWy0G6yZpgqsU8o/xYqOEWa8O6nnu8dXEcKe9LuH5ScBJolt+r+8QXgovqETGSvEoYU MX2piL1bTtc7K6QjR/GvDVUYSrMG6tPXlRxp2LH6Cwzj4ynpII6VnQpMMe1xtSYrgj3yyt JxTChlnyFuk5ONMDbdygpZq3RR2ZDU0= X-MC-Unique: N94jPjuOP1O1N2kdWLa0VA-1 From: Eduardo Habkost To: qemu-devel@nongnu.org Subject: [PATCH v4 1/2] sifive_e: Rename memmap enum constants Date: Fri, 11 Sep 2020 13:34:46 -0400 Message-Id: <20200911173447.165713-2-ehabkost@redhat.com> In-Reply-To: <20200911173447.165713-1-ehabkost@redhat.com> References: <20200911173447.165713-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0.001 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Berrange" , qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Some of the enum constant names conflict with a QOM type check macro (SIFIVE_E_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost Reviewed-by: Alistair Francis --- Changes v3 -> v4: * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910 Link to v3: https://lore.kernel.org/qemu-devel/20200825192110.3528606-9-ehabkost@redhat= .com/ Changes v2 -> v3: none Changes v1 -> v2: * Added more details to commit message --- Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org --- include/hw/riscv/sifive_e.h | 38 ++++++++--------- hw/riscv/sifive_e.c | 82 ++++++++++++++++++------------------- 2 files changed, 60 insertions(+), 60 deletions(-) diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index b1400843c2..83604da805 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -53,25 +53,25 @@ typedef struct SiFiveEState { OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE) =20 enum { - SIFIVE_E_DEBUG, - SIFIVE_E_MROM, - SIFIVE_E_OTP, - SIFIVE_E_CLINT, - SIFIVE_E_PLIC, - SIFIVE_E_AON, - SIFIVE_E_PRCI, - SIFIVE_E_OTP_CTRL, - SIFIVE_E_GPIO0, - SIFIVE_E_UART0, - SIFIVE_E_QSPI0, - SIFIVE_E_PWM0, - SIFIVE_E_UART1, - SIFIVE_E_QSPI1, - SIFIVE_E_PWM1, - SIFIVE_E_QSPI2, - SIFIVE_E_PWM2, - SIFIVE_E_XIP, - SIFIVE_E_DTIM + SIFIVE_E_DEV_DEBUG, + SIFIVE_E_DEV_MROM, + SIFIVE_E_DEV_OTP, + SIFIVE_E_DEV_CLINT, + SIFIVE_E_DEV_PLIC, + SIFIVE_E_DEV_AON, + SIFIVE_E_DEV_PRCI, + SIFIVE_E_DEV_OTP_CTRL, + SIFIVE_E_DEV_GPIO0, + SIFIVE_E_DEV_UART0, + SIFIVE_E_DEV_QSPI0, + SIFIVE_E_DEV_PWM0, + SIFIVE_E_DEV_UART1, + SIFIVE_E_DEV_QSPI1, + SIFIVE_E_DEV_PWM1, + SIFIVE_E_DEV_QSPI2, + SIFIVE_E_DEV_PWM2, + SIFIVE_E_DEV_XIP, + SIFIVE_E_DEV_DTIM }; =20 enum { diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 40bbf530d4..759059cd7b 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -54,25 +54,25 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_e_memmap[] =3D { - [SIFIVE_E_DEBUG] =3D { 0x0, 0x1000 }, - [SIFIVE_E_MROM] =3D { 0x1000, 0x2000 }, - [SIFIVE_E_OTP] =3D { 0x20000, 0x2000 }, - [SIFIVE_E_CLINT] =3D { 0x2000000, 0x10000 }, - [SIFIVE_E_PLIC] =3D { 0xc000000, 0x4000000 }, - [SIFIVE_E_AON] =3D { 0x10000000, 0x8000 }, - [SIFIVE_E_PRCI] =3D { 0x10008000, 0x8000 }, - [SIFIVE_E_OTP_CTRL] =3D { 0x10010000, 0x1000 }, - [SIFIVE_E_GPIO0] =3D { 0x10012000, 0x1000 }, - [SIFIVE_E_UART0] =3D { 0x10013000, 0x1000 }, - [SIFIVE_E_QSPI0] =3D { 0x10014000, 0x1000 }, - [SIFIVE_E_PWM0] =3D { 0x10015000, 0x1000 }, - [SIFIVE_E_UART1] =3D { 0x10023000, 0x1000 }, - [SIFIVE_E_QSPI1] =3D { 0x10024000, 0x1000 }, - [SIFIVE_E_PWM1] =3D { 0x10025000, 0x1000 }, - [SIFIVE_E_QSPI2] =3D { 0x10034000, 0x1000 }, - [SIFIVE_E_PWM2] =3D { 0x10035000, 0x1000 }, - [SIFIVE_E_XIP] =3D { 0x20000000, 0x20000000 }, - [SIFIVE_E_DTIM] =3D { 0x80000000, 0x4000 } + [SIFIVE_E_DEV_DEBUG] =3D { 0x0, 0x1000 }, + [SIFIVE_E_DEV_MROM] =3D { 0x1000, 0x2000 }, + [SIFIVE_E_DEV_OTP] =3D { 0x20000, 0x2000 }, + [SIFIVE_E_DEV_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_E_DEV_PLIC] =3D { 0xc000000, 0x4000000 }, + [SIFIVE_E_DEV_AON] =3D { 0x10000000, 0x8000 }, + [SIFIVE_E_DEV_PRCI] =3D { 0x10008000, 0x8000 }, + [SIFIVE_E_DEV_OTP_CTRL] =3D { 0x10010000, 0x1000 }, + [SIFIVE_E_DEV_GPIO0] =3D { 0x10012000, 0x1000 }, + [SIFIVE_E_DEV_UART0] =3D { 0x10013000, 0x1000 }, + [SIFIVE_E_DEV_QSPI0] =3D { 0x10014000, 0x1000 }, + [SIFIVE_E_DEV_PWM0] =3D { 0x10015000, 0x1000 }, + [SIFIVE_E_DEV_UART1] =3D { 0x10023000, 0x1000 }, + [SIFIVE_E_DEV_QSPI1] =3D { 0x10024000, 0x1000 }, + [SIFIVE_E_DEV_PWM1] =3D { 0x10025000, 0x1000 }, + [SIFIVE_E_DEV_QSPI2] =3D { 0x10034000, 0x1000 }, + [SIFIVE_E_DEV_PWM2] =3D { 0x10035000, 0x1000 }, + [SIFIVE_E_DEV_XIP] =3D { 0x20000000, 0x20000000 }, + [SIFIVE_E_DEV_DTIM] =3D { 0x80000000, 0x4000 } }; =20 static void sifive_e_machine_init(MachineState *machine) @@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine) =20 /* Data Tightly Integrated Memory */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram", - memmap[SIFIVE_E_DTIM].size, &error_fatal); + memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_DTIM].base, main_mem); + memmap[SIFIVE_E_DEV_DTIM].base, main_mem); =20 /* Mask ROM reset vector */ uint32_t reset_vec[4]; @@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine) reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SIFIVE_E_MROM].base, &address_space_memor= y); + memmap[SIFIVE_E_DEV_MROM].base, &address_space_m= emory); =20 if (machine->kernel_filename) { riscv_load_kernel(machine->kernel_filename, NULL); @@ -195,12 +195,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) =20 /* Mask ROM */ memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom= ", - memmap[SIFIVE_E_MROM].size, &error_fatal); + memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); memory_region_add_subregion(sys_mem, - memmap[SIFIVE_E_MROM].base, &s->mask_rom); + memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_E_PLIC].base, + s->plic =3D sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, (char *)SIFIVE_E_PLIC_HART_CONFIG, 0, SIFIVE_E_PLIC_NUM_SOURCES, SIFIVE_E_PLIC_NUM_PRIORITIES, @@ -210,14 +210,14 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) SIFIVE_E_PLIC_ENABLE_STRIDE, SIFIVE_E_PLIC_CONTEXT_BASE, SIFIVE_E_PLIC_CONTEXT_STRIDE, - memmap[SIFIVE_E_PLIC].size); - sifive_clint_create(memmap[SIFIVE_E_CLINT].base, - memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, + memmap[SIFIVE_E_DEV_PLIC].size); + sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base, + memmap[SIFIVE_E_DEV_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); create_unimplemented_device("riscv.sifive.e.aon", - memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); + memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size); + sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base); =20 /* GPIO */ =20 @@ -226,7 +226,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* Map GPIO registers */ - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].ba= se); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0= ].base); =20 /* Pass all GPIOs to the SOC layer so they are available to the board = */ qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); @@ -238,27 +238,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Er= ror **errp) SIFIVE_E_GPIO0_IRQ0 + i)); } =20 - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ= )); create_unimplemented_device("riscv.sifive.e.qspi0", - memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); + memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size); create_unimplemented_device("riscv.sifive.e.pwm0", - memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); - sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, + memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size); + sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ= )); create_unimplemented_device("riscv.sifive.e.qspi1", - memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); + memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size); create_unimplemented_device("riscv.sifive.e.pwm1", - memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); + memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size); create_unimplemented_device("riscv.sifive.e.qspi2", - memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); + memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size); create_unimplemented_device("riscv.sifive.e.pwm2", - memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); + memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size); =20 /* Flash memory */ memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip", - memmap[SIFIVE_E_XIP].size, &error_fatal); - memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base, + memmap[SIFIVE_E_DEV_XIP].size, &error_fatal); + memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base, &s->xip_mem); } =20 --=20 2.26.2 From nobody Sat Feb 7 03:37:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1599845772; cv=none; d=zohomail.com; s=zohoarc; b=XZDx8UXr0wl3FIWPyUCK4lxQgJr+AMVBiPL8REVEfltw8NXEXCzCpYphz8Mdx7tE7Wc3lOSK/odE24T/41EJi85Z2rZo+p3U1dewiigRL5vW7RV1zXwdglyWqvEqvvsSab21F/M+HqBw9zZlLk7tCZdxGZJWwdveweotDKimS/E= ARC-Message-Signature: i=1; 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auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=ehabkost@redhat.com X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.120; envelope-from=ehabkost@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/11 09:43:46 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P. Berrange" , qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Alistair Francis , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Some of the enum constant names conflict with the QOM type check macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE(). Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts. Signed-off-by: Eduardo Habkost Reviewed-by: Alistair Francis --- Changes v3 -> v4: * Patch recreated, rebased to tags/pull-riscv-to-apply-20200910 Link to v3: https://lore.kernel.org/qemu-devel/20200825192110.3528606-10-ehabkost@redha= t.com/ Changes v2 -> v3: * Solved conflicts on rebase to latest qemu.git * As this is a new patch, Reviewed-by lines from Alistair Francis and Daniel P. Berrang=C3=A9 were dropped Changes v1 -> v2: * Added more details to commit message --- Cc: Palmer Dabbelt Cc: Alistair Francis Cc: Sagar Karandikar Cc: Bastian Koppelmann Cc: qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org --- include/hw/riscv/sifive_u.h | 34 ++++---- hw/riscv/sifive_u.c | 156 ++++++++++++++++++------------------ 2 files changed, 95 insertions(+), 95 deletions(-) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index fe5c580845..22e7e6efa1 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -70,23 +70,23 @@ typedef struct SiFiveUState { } SiFiveUState; =20 enum { - SIFIVE_U_DEBUG, - SIFIVE_U_MROM, - SIFIVE_U_CLINT, - SIFIVE_U_L2CC, - SIFIVE_U_PDMA, - SIFIVE_U_L2LIM, - SIFIVE_U_PLIC, - SIFIVE_U_PRCI, - SIFIVE_U_UART0, - SIFIVE_U_UART1, - SIFIVE_U_GPIO, - SIFIVE_U_OTP, - SIFIVE_U_DMC, - SIFIVE_U_FLASH0, - SIFIVE_U_DRAM, - SIFIVE_U_GEM, - SIFIVE_U_GEM_MGMT + SIFIVE_U_DEV_DEBUG, + SIFIVE_U_DEV_MROM, + SIFIVE_U_DEV_CLINT, + SIFIVE_U_DEV_L2CC, + SIFIVE_U_DEV_PDMA, + SIFIVE_U_DEV_L2LIM, + SIFIVE_U_DEV_PLIC, + SIFIVE_U_DEV_PRCI, + SIFIVE_U_DEV_UART0, + SIFIVE_U_DEV_UART1, + SIFIVE_U_DEV_GPIO, + SIFIVE_U_DEV_OTP, + SIFIVE_U_DEV_DMC, + SIFIVE_U_DEV_FLASH0, + SIFIVE_U_DEV_DRAM, + SIFIVE_U_DEV_GEM, + SIFIVE_U_DEV_GEM_MGMT }; =20 enum { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 4f12a93188..a97637fb33 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -70,23 +70,23 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } sifive_u_memmap[] =3D { - [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, - [SIFIVE_U_MROM] =3D { 0x1000, 0xf000 }, - [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, - [SIFIVE_U_L2CC] =3D { 0x2010000, 0x1000 }, - [SIFIVE_U_PDMA] =3D { 0x3000000, 0x100000 }, - [SIFIVE_U_L2LIM] =3D { 0x8000000, 0x2000000 }, - [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, - [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, - [SIFIVE_U_UART0] =3D { 0x10010000, 0x1000 }, - [SIFIVE_U_UART1] =3D { 0x10011000, 0x1000 }, - [SIFIVE_U_GPIO] =3D { 0x10060000, 0x1000 }, - [SIFIVE_U_OTP] =3D { 0x10070000, 0x1000 }, - [SIFIVE_U_GEM] =3D { 0x10090000, 0x2000 }, - [SIFIVE_U_GEM_MGMT] =3D { 0x100a0000, 0x1000 }, - [SIFIVE_U_DMC] =3D { 0x100b0000, 0x10000 }, - [SIFIVE_U_FLASH0] =3D { 0x20000000, 0x10000000 }, - [SIFIVE_U_DRAM] =3D { 0x80000000, 0x0 }, + [SIFIVE_U_DEV_DEBUG] =3D { 0x0, 0x100 }, + [SIFIVE_U_DEV_MROM] =3D { 0x1000, 0xf000 }, + [SIFIVE_U_DEV_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_U_DEV_L2CC] =3D { 0x2010000, 0x1000 }, + [SIFIVE_U_DEV_PDMA] =3D { 0x3000000, 0x100000 }, + [SIFIVE_U_DEV_L2LIM] =3D { 0x8000000, 0x2000000 }, + [SIFIVE_U_DEV_PLIC] =3D { 0xc000000, 0x4000000 }, + [SIFIVE_U_DEV_PRCI] =3D { 0x10000000, 0x1000 }, + [SIFIVE_U_DEV_UART0] =3D { 0x10010000, 0x1000 }, + [SIFIVE_U_DEV_UART1] =3D { 0x10011000, 0x1000 }, + [SIFIVE_U_DEV_GPIO] =3D { 0x10060000, 0x1000 }, + [SIFIVE_U_DEV_OTP] =3D { 0x10070000, 0x1000 }, + [SIFIVE_U_DEV_GEM] =3D { 0x10090000, 0x2000 }, + [SIFIVE_U_DEV_GEM_MGMT] =3D { 0x100a0000, 0x1000 }, + [SIFIVE_U_DEV_DMC] =3D { 0x100b0000, 0x10000 }, + [SIFIVE_U_DEV_FLASH0] =3D { 0x20000000, 0x10000000 }, + [SIFIVE_U_DEV_DRAM] =3D { 0x80000000, 0x0 }, }; =20 #define OTP_SERIAL 1 @@ -145,10 +145,10 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, g_free(nodename); =20 nodename =3D g_strdup_printf("/memory@%lx", - (long)memmap[SIFIVE_U_DRAM].base); + (long)memmap[SIFIVE_U_DEV_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cells(fdt, nodename, "reg", - memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base, + memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].ba= se, mem_size >> 32, mem_size); qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); g_free(nodename); @@ -203,39 +203,39 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, g_free(nodename); } nodename =3D g_strdup_printf("/soc/clint@%lx", - (long)memmap[SIFIVE_U_CLINT].base); + (long)memmap[SIFIVE_U_DEV_CLINT].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0"); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_CLINT].base, - 0x0, memmap[SIFIVE_U_CLINT].size); + 0x0, memmap[SIFIVE_U_DEV_CLINT].base, + 0x0, memmap[SIFIVE_U_DEV_CLINT].size); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, ms->smp.cpus * sizeof(uint32_t) * 4); g_free(cells); g_free(nodename); =20 nodename =3D g_strdup_printf("/soc/otp@%lx", - (long)memmap[SIFIVE_U_OTP].base); + (long)memmap[SIFIVE_U_DEV_OTP].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SI= ZE); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_OTP].base, - 0x0, memmap[SIFIVE_U_OTP].size); + 0x0, memmap[SIFIVE_U_DEV_OTP].base, + 0x0, memmap[SIFIVE_U_DEV_OTP].size); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,fu540-c000-otp"); g_free(nodename); =20 prci_phandle =3D phandle++; nodename =3D g_strdup_printf("/soc/clock-controller@%lx", - (long)memmap[SIFIVE_U_PRCI].base); + (long)memmap[SIFIVE_U_DEV_PRCI].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); qemu_fdt_setprop_cells(fdt, nodename, "clocks", hfclk_phandle, rtcclk_phandle); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_PRCI].base, - 0x0, memmap[SIFIVE_U_PRCI].size); + 0x0, memmap[SIFIVE_U_DEV_PRCI].base, + 0x0, memmap[SIFIVE_U_DEV_PRCI].size); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,fu540-c000-prci"); g_free(nodename); @@ -259,7 +259,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); } nodename =3D g_strdup_printf("/soc/interrupt-controller@%lx", - (long)memmap[SIFIVE_U_PLIC].base); + (long)memmap[SIFIVE_U_DEV_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); @@ -267,8 +267,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, qemu_fdt_setprop(fdt, nodename, "interrupts-extended", cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_PLIC].base, - 0x0, memmap[SIFIVE_U_PLIC].size); + 0x0, memmap[SIFIVE_U_DEV_PLIC].base, + 0x0, memmap[SIFIVE_U_DEV_PLIC].size); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle =3D qemu_fdt_get_phandle(fdt, nodename); @@ -277,7 +277,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, =20 gpio_phandle =3D phandle++; nodename =3D g_strdup_printf("/soc/gpio@%lx", - (long)memmap[SIFIVE_U_GPIO].base); + (long)memmap[SIFIVE_U_DEV_GPIO].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle); qemu_fdt_setprop_cells(fdt, nodename, "clocks", @@ -287,8 +287,8 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2); qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_GPIO].base, - 0x0, memmap[SIFIVE_U_GPIO].size); + 0x0, memmap[SIFIVE_U_DEV_GPIO].base, + 0x0, memmap[SIFIVE_U_DEV_GPIO].size); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0, SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3, SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6, @@ -306,7 +306,7 @@ static void create_fdt(SiFiveUState *s, const struct Me= mmapEntry *memmap, g_free(nodename); =20 nodename =3D g_strdup_printf("/soc/dma@%lx", - (long)memmap[SIFIVE_U_PDMA].base); + (long)memmap[SIFIVE_U_DEV_PDMA].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", @@ -315,18 +315,18 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_PDMA].base, - 0x0, memmap[SIFIVE_U_PDMA].size); + 0x0, memmap[SIFIVE_U_DEV_PDMA].base, + 0x0, memmap[SIFIVE_U_DEV_PDMA].size); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,fu540-c000-pdma"); g_free(nodename); =20 nodename =3D g_strdup_printf("/soc/cache-controller@%lx", - (long)memmap[SIFIVE_U_L2CC].base); + (long)memmap[SIFIVE_U_DEV_L2CC].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_L2CC].base, - 0x0, memmap[SIFIVE_U_L2CC].size); + 0x0, memmap[SIFIVE_U_DEV_L2CC].base, + 0x0, memmap[SIFIVE_U_DEV_L2CC].size); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); @@ -341,15 +341,15 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, =20 phy_phandle =3D phandle++; nodename =3D g_strdup_printf("/soc/ethernet@%lx", - (long)memmap[SIFIVE_U_GEM].base); + (long)memmap[SIFIVE_U_DEV_GEM].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,fu540-c000-gem"); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_GEM].base, - 0x0, memmap[SIFIVE_U_GEM].size, - 0x0, memmap[SIFIVE_U_GEM_MGMT].base, - 0x0, memmap[SIFIVE_U_GEM_MGMT].size); + 0x0, memmap[SIFIVE_U_DEV_GEM].base, + 0x0, memmap[SIFIVE_U_DEV_GEM].size, + 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base, + 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size); qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); @@ -370,19 +370,19 @@ static void create_fdt(SiFiveUState *s, const struct = MemmapEntry *memmap, g_free(nodename); =20 nodename =3D g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", - (long)memmap[SIFIVE_U_GEM].base); + (long)memmap[SIFIVE_U_DEV_GEM].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); =20 nodename =3D g_strdup_printf("/soc/serial@%lx", - (long)memmap[SIFIVE_U_UART0].base); + (long)memmap[SIFIVE_U_DEV_UART0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); qemu_fdt_setprop_cells(fdt, nodename, "reg", - 0x0, memmap[SIFIVE_U_UART0].base, - 0x0, memmap[SIFIVE_U_UART0].size); + 0x0, memmap[SIFIVE_U_DEV_UART0].base, + 0x0, memmap[SIFIVE_U_DEV_UART0].size); qemu_fdt_setprop_cells(fdt, nodename, "clocks", prci_phandle, PRCI_CLK_TLCLK); qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); @@ -414,7 +414,7 @@ static void sifive_u_machine_init(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); MemoryRegion *flash0 =3D g_new(MemoryRegion, 1); - target_ulong start_addr =3D memmap[SIFIVE_U_DRAM].base; + target_ulong start_addr =3D memmap[SIFIVE_U_DEV_DRAM].base; uint32_t start_addr_hi32 =3D 0x00000000; int i; uint32_t fdt_load_addr; @@ -429,13 +429,13 @@ static void sifive_u_machine_init(MachineState *machi= ne) /* register RAM */ memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram", machine->ram_size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].b= ase, main_mem); =20 /* register QSPI0 Flash */ memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", - memmap[SIFIVE_U_FLASH0].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].bas= e, + memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0]= .base, flash0); =20 /* register gpio-restart */ @@ -461,14 +461,14 @@ static void sifive_u_machine_init(MachineState *machi= ne) =20 switch (s->msel) { case MSEL_MEMMAP_QSPI0_FLASH: - start_addr =3D memmap[SIFIVE_U_FLASH0].base; + start_addr =3D memmap[SIFIVE_U_DEV_FLASH0].base; break; case MSEL_L2LIM_QSPI0_FLASH: case MSEL_L2LIM_QSPI2_SD: - start_addr =3D memmap[SIFIVE_U_L2LIM].base; + start_addr =3D memmap[SIFIVE_U_DEV_L2LIM].base; break; default: - start_addr =3D memmap[SIFIVE_U_DRAM].base; + start_addr =3D memmap[SIFIVE_U_DEV_DRAM].base; break; } =20 @@ -496,7 +496,7 @@ static void sifive_u_machine_init(MachineState *machine) } =20 /* Compute the fdt load address in dram */ - fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DRAM].base, + fdt_load_addr =3D riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, machine->ram_size, s->fdt); #if defined(TARGET_RISCV64) start_addr_hi32 =3D start_addr >> 32; @@ -528,10 +528,10 @@ static void sifive_u_machine_init(MachineState *machi= ne) reset_vec[i] =3D cpu_to_le32(reset_vec[i]); } rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SIFIVE_U_MROM].base, &address_space_memor= y); + memmap[SIFIVE_U_DEV_MROM].base, &address_space_m= emory); =20 - riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base, - memmap[SIFIVE_U_MROM].size, + riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base, + memmap[SIFIVE_U_DEV_MROM].size, sizeof(reset_vec), kernel_entry); } =20 @@ -674,8 +674,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) =20 /* boot rom */ memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom", - memmap[SIFIVE_U_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + memmap[SIFIVE_U_DEV_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].b= ase, mask_rom); =20 /* @@ -688,8 +688,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) * too generous to misbehaving guests. */ memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", - memmap[SIFIVE_U_L2LIM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, + memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].= base, l2lim_mem); =20 /* create PLIC hart topology configuration string */ @@ -707,7 +707,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) } =20 /* MMIO */ - s->plic =3D sifive_plic_create(memmap[SIFIVE_U_PLIC].base, + s->plic =3D sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base, plic_hart_config, 0, SIFIVE_U_PLIC_NUM_SOURCES, SIFIVE_U_PLIC_NUM_PRIORITIES, @@ -717,27 +717,27 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) SIFIVE_U_PLIC_ENABLE_STRIDE, SIFIVE_U_PLIC_CONTEXT_BASE, SIFIVE_U_PLIC_CONTEXT_STRIDE, - memmap[SIFIVE_U_PLIC].size); + memmap[SIFIVE_U_DEV_PLIC].size); g_free(plic_hart_config); - sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, + sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ= )); - sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, + sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); - sifive_clint_create(memmap[SIFIVE_U_CLINT].base, - memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, + sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base, + memmap[SIFIVE_U_DEV_CLINT].size, 0, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, SIFIVE_CLINT_TIMEBASE_FREQ, false); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].bas= e); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI]= .base); =20 qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].bas= e); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO]= .base); =20 /* Pass all GPIOs to the SOC layer so they are available to the board = */ qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL); @@ -751,7 +751,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) =20 /* PDMA */ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); - sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base= ); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_DEV_PDMA].= base); =20 /* Connect PDMA interrupts to the PLIC */ for (i =3D 0; i < SIFIVE_PDMA_IRQS; i++) { @@ -764,7 +764,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].b= ase); =20 /* FIXME use qdev NIC properties instead of nd_table[] */ if (nd->used) { @@ -776,18 +776,18 @@ static void sifive_u_soc_realize(DeviceState *dev, Er= ror **errp) if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) { return; } - sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].b= ase); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ)= ); =20 create_unimplemented_device("riscv.sifive.u.gem-mgmt", - memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); + memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].= size); =20 create_unimplemented_device("riscv.sifive.u.dmc", - memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size); + memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size); =20 create_unimplemented_device("riscv.sifive.u.l2cc", - memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size); + memmap[SIFIVE_U_DEV_L2CC].base, memmap[SIFIVE_U_DEV_L2CC].size); } =20 static Property sifive_u_soc_props[] =3D { --=20 2.26.2