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From: Alistair Francis <alistair.francis@wdc.com>
To: peter.maydell@linaro.org,
qemu-devel@nongnu.org
Subject: [PULL 12/30] hw/riscv: microchip_pfsoc: Connect a DMA controller
Date: Thu, 10 Sep 2020 11:09:20 -0700
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From: Bin Meng <bin.meng@windriver.com>
On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA
controller to move the 2nd stage bootloader in the system memory.
Let's connect a DMA controller to Microchip PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1598924352-89526-11-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++
hw/riscv/microchip_pfsoc.c | 15 +++++++++++++++
hw/riscv/Kconfig | 1 +
3 files changed, 27 insertions(+)
diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi=
p_pfsoc.h
index d810ee8484..63e786052a 100644
--- a/include/hw/riscv/microchip_pfsoc.h
+++ b/include/hw/riscv/microchip_pfsoc.h
@@ -23,6 +23,7 @@
#define HW_MICROCHIP_PFSOC_H
=20
#include "hw/char/mchp_pfsoc_mmuart.h"
+#include "hw/dma/sifive_pdma.h"
#include "hw/sd/cadence_sdhci.h"
=20
typedef struct MicrochipPFSoCState {
@@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState {
MchpPfSoCMMUartState *serial2;
MchpPfSoCMMUartState *serial3;
MchpPfSoCMMUartState *serial4;
+ SiFivePDMAState dma;
CadenceSDHCIState sdhci;
} MicrochipPFSoCState;
=20
@@ -71,6 +73,7 @@ enum {
MICROCHIP_PFSOC_BUSERR_UNIT4,
MICROCHIP_PFSOC_CLINT,
MICROCHIP_PFSOC_L2CC,
+ MICROCHIP_PFSOC_DMA,
MICROCHIP_PFSOC_L2LIM,
MICROCHIP_PFSOC_PLIC,
MICROCHIP_PFSOC_MMUART0,
@@ -88,6 +91,14 @@ enum {
};
=20
enum {
+ MICROCHIP_PFSOC_DMA_IRQ0 =3D 5,
+ MICROCHIP_PFSOC_DMA_IRQ1 =3D 6,
+ MICROCHIP_PFSOC_DMA_IRQ2 =3D 7,
+ MICROCHIP_PFSOC_DMA_IRQ3 =3D 8,
+ MICROCHIP_PFSOC_DMA_IRQ4 =3D 9,
+ MICROCHIP_PFSOC_DMA_IRQ5 =3D 10,
+ MICROCHIP_PFSOC_DMA_IRQ6 =3D 11,
+ MICROCHIP_PFSOC_DMA_IRQ7 =3D 12,
MICROCHIP_PFSOC_EMMC_SD_IRQ =3D 88,
MICROCHIP_PFSOC_MMUART0_IRQ =3D 90,
MICROCHIP_PFSOC_MMUART1_IRQ =3D 91,
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 0b2e9ca175..d8ec973958 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -13,6 +13,7 @@
* 2) eNVM (Embedded Non-Volatile Memory)
* 3) MMUARTs (Multi-Mode UART)
* 4) Cadence eMMC/SDHC controller and an SD card connected to it
+ * 5) SiFive Platform DMA (Direct Memory Access Controller)
*
* This board currently generates devicetree dynamically that indicates at=
least
* two harts and up to five harts.
@@ -71,6 +72,7 @@ static const struct MemmapEntry {
[MICROCHIP_PFSOC_BUSERR_UNIT4] =3D { 0x1704000, 0x1000 },
[MICROCHIP_PFSOC_CLINT] =3D { 0x2000000, 0x10000 },
[MICROCHIP_PFSOC_L2CC] =3D { 0x2010000, 0x1000 },
+ [MICROCHIP_PFSOC_DMA] =3D { 0x3000000, 0x100000 },
[MICROCHIP_PFSOC_L2LIM] =3D { 0x8000000, 0x2000000 },
[MICROCHIP_PFSOC_PLIC] =3D { 0xc000000, 0x4000000 },
[MICROCHIP_PFSOC_MMUART0] =3D { 0x20000000, 0x1000 },
@@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *o=
bj)
TYPE_RISCV_CPU_SIFIVE_U54);
qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR);
=20
+ object_initialize_child(obj, "dma-controller", &s->dma,
+ TYPE_SIFIVE_PDMA);
+
object_initialize_child(obj, "sd-controller", &s->sdhci,
TYPE_CADENCE_SDHCI);
}
@@ -218,6 +223,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *d=
ev, Error **errp)
memmap[MICROCHIP_PFSOC_PLIC].size);
g_free(plic_hart_config);
=20
+ /* DMA */
+ sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0,
+ memmap[MICROCHIP_PFSOC_DMA].base);
+ for (i =3D 0; i < SIFIVE_PDMA_IRQS; i++) {
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i,
+ qdev_get_gpio_in(DEVICE(s->plic),
+ MICROCHIP_PFSOC_DMA_IRQ0 + i));
+ }
+
/* SYSREG */
create_unimplemented_device("microchip.pfsoc.sysreg",
memmap[MICROCHIP_PFSOC_SYSREG].base,
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
index 7412db9ad7..9032cb0cbd 100644
--- a/hw/riscv/Kconfig
+++ b/hw/riscv/Kconfig
@@ -55,4 +55,5 @@ config MICROCHIP_PFSOC
select SIFIVE
select UNIMP
select MCHP_PFSOC_MMUART
+ select SIFIVE_PDMA
select CADENCE_SDHCI
--=20
2.28.0