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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q186sm4603128wma.45.2020.09.10.10.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 10:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yrb435SyHhRGm1EucboctVOMgvMxS5WyjB6BP+Kvcd0=; b=aRJZoQECV3V+9Om8kMKrD61gHhCIOwhhv4/7pKpind93deQArKPxJZHSDyByWCwL2m Z1kf8ohN3bJnOw+9sDlIJDZsYgLAFH8bVQN+Qc2VxkGB61iaEo2xmNE+uJkytJwr/qDC C/1YDTVAdG7JhyMcuCeOa3C1HuZmd71WTFFHkEd/6HOHRaSakLgz/p14TTxOTkdBNduJ LmjNnKMGeb5owvIhtzZHu5sL6SpURvkhx9kCidu51+1ox0IFE+kZCsE0l7G0uCtaPtY0 Bdn8bUiVWJ3HsXFmm8vLd1/VpfR4UcY6nQKK+UROroeC9WkAw9hkyZiF+za2D0DxZRcg ZiNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yrb435SyHhRGm1EucboctVOMgvMxS5WyjB6BP+Kvcd0=; b=a971Tz6q9wC3XPUWb71ly7QMl6WuGVF3FPHK4gOtIXP1s+XS78e/ZFwFBSeV7Ion2E y3ppstZ5dHhI+o7/2w6zhN1Qv6nrs8tGpHs/ium2DHwMLCyPrJjrjc5gF+zLqhZskRib lmwxFNqLSrS371SzTF14CK90Mqd5L8o2QnkGIdJZnzE7AywpJv7v+tPK0hw3yEdh3XdD 1d5x1jUdfO5xp5Tv+m1y/RusQmfB7uBYK87WoRF3M+TK9BtkNv6IZpLLG1i3zfYgiorD wmSWZR7KqQrnNNHQG7h0Apthfb4EimW3axWqLlptZ6LOJO+6X4EiUyoVyQd14fTYGq6q OSYg== X-Gm-Message-State: AOAM533LgkFBHoyO4LVku2meQcYujbmzARp7buZ5/ynyLHmLCjfxauws qywpRJr11IBjGk85m2YW3JaIU1Gml59CNC2A X-Google-Smtp-Source: ABdhPJwysux6giTy3tYdt7Z2nZVkEgydjb+8D1NYocjIh9+yP//sp5gssNrUxfvnhqGcCMQo7PPkzg== X-Received: by 2002:a5d:4e0b:: with SMTP id p11mr9983889wrt.32.1599759541467; Thu, 10 Sep 2020 10:39:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check Date: Thu, 10 Sep 2020 18:38:51 +0100 Message-Id: <20200910173855.4068-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200910173855.4068-1-peter.maydell@linaro.org> References: <20200910173855.4068-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN bit in short-descriptor translation table format descriptors. This is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the feature bit with an ID register check, in line with our preference for ID register checks over feature bits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 15 ++++++++++++++- target/arm/cpu.c | 1 - target/arm/helper.c | 5 +++-- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a1c7d8ebae5..b7c2615b2fe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1775,6 +1775,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) =20 +FIELD(ID_MMFR0, VMSA, 0, 4) +FIELD(ID_MMFR0, PMSA, 4, 4) +FIELD(ID_MMFR0, OUTERSHR, 8, 4) +FIELD(ID_MMFR0, SHARELVL, 12, 4) +FIELD(ID_MMFR0, TCM, 16, 4) +FIELD(ID_MMFR0, AUXREG, 20, 4) +FIELD(ID_MMFR0, FCSE, 24, 4) +FIELD(ID_MMFR0, INNERSHR, 28, 4) + FIELD(ID_MMFR3, CMAINTVA, 0, 4) FIELD(ID_MMFR3, CMAINTSW, 4, 4) FIELD(ID_MMFR3, BPMAINT, 8, 4) @@ -1952,7 +1961,6 @@ enum arm_features { ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register = */ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ - ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ ARM_FEATURE_V8, ARM_FEATURE_AARCH64, /* supports 64 bit mode */ @@ -3618,6 +3626,11 @@ static inline bool isar_feature_aa32_vminmaxnm(const= ARMISARegisters *id) return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 +static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >=3D 4; +} + static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c179e0752da..c5e86ce50af 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1589,7 +1589,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } if (arm_feature(env, ARM_FEATURE_LPAE)) { set_feature(env, ARM_FEATURE_V7MP); - set_feature(env, ARM_FEATURE_PXN); } if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { set_feature(env, ARM_FEATURE_CBAR); diff --git a/target/arm/helper.c b/target/arm/helper.c index 44d666627a8..ef6eaf6450f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10537,6 +10537,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -10563,7 +10564,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, goto do_fault; } type =3D (desc & 3); - if (type =3D=3D 0 || (type =3D=3D 3 && !arm_feature(env, ARM_FEATURE_P= XN))) { + if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { /* Section translation fault, or attempt to use the encoding * which is Reserved on implementations without PXN. */ @@ -10605,7 +10606,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, pxn =3D desc & 1; ns =3D extract32(desc, 19, 1); } else { - if (arm_feature(env, ARM_FEATURE_PXN)) { + if (cpu_isar_feature(aa32_pxn, cpu)) { pxn =3D (desc >> 2) & 1; } ns =3D extract32(desc, 3, 1); --=20 2.20.1