From nobody Thu May 2 10:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599759621; cv=none; d=zohomail.com; s=zohoarc; b=JM5PPgtGLRTCrz/8dh3KsKA20XD/yQgfbDQjomKq4jJ0tQAVBG6Is7TTVwNC5JjcShnYEdYSxJWa4iF+FrXee4thEJkyjOAW/cfWi9Kji7FnesFQj5UUcqc0uyf3VX0nmfITx+rPDEy3GqcG0yrSv37AOs/9QJmsOKOAhICniJQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599759621; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yrb435SyHhRGm1EucboctVOMgvMxS5WyjB6BP+Kvcd0=; b=dFbFXIZlqcLXyXwuuU29RGJF8dlfFSkNsa9nZOBjI8VHbEfObKzh8A9dBNF4URT1mV1KOymumhWJm4QEl3IexxMpYDyqkvZvO2trInID59SayzOYa5KiNJJzaMKZbKzL0/vs+7pRRFsSpXVi5xwFN6Uoj3oNc45XUWYEfyStRtU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159975962173394.79806378169155; Thu, 10 Sep 2020 10:40:21 -0700 (PDT) Received: from localhost ([::1]:39780 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kGQYW-0005mV-8y for importer@patchew.org; Thu, 10 Sep 2020 13:40:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44550) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kGQXM-0003tj-6H for qemu-devel@nongnu.org; Thu, 10 Sep 2020 13:39:08 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:34710) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kGQXJ-0002nJ-Lg for qemu-devel@nongnu.org; Thu, 10 Sep 2020 13:39:07 -0400 Received: by mail-wr1-x441.google.com with SMTP id t10so7738343wrv.1 for ; Thu, 10 Sep 2020 10:39:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q186sm4603128wma.45.2020.09.10.10.38.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 10:39:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yrb435SyHhRGm1EucboctVOMgvMxS5WyjB6BP+Kvcd0=; b=aRJZoQECV3V+9Om8kMKrD61gHhCIOwhhv4/7pKpind93deQArKPxJZHSDyByWCwL2m Z1kf8ohN3bJnOw+9sDlIJDZsYgLAFH8bVQN+Qc2VxkGB61iaEo2xmNE+uJkytJwr/qDC C/1YDTVAdG7JhyMcuCeOa3C1HuZmd71WTFFHkEd/6HOHRaSakLgz/p14TTxOTkdBNduJ LmjNnKMGeb5owvIhtzZHu5sL6SpURvkhx9kCidu51+1ox0IFE+kZCsE0l7G0uCtaPtY0 Bdn8bUiVWJ3HsXFmm8vLd1/VpfR4UcY6nQKK+UROroeC9WkAw9hkyZiF+za2D0DxZRcg ZiNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yrb435SyHhRGm1EucboctVOMgvMxS5WyjB6BP+Kvcd0=; b=a971Tz6q9wC3XPUWb71ly7QMl6WuGVF3FPHK4gOtIXP1s+XS78e/ZFwFBSeV7Ion2E y3ppstZ5dHhI+o7/2w6zhN1Qv6nrs8tGpHs/ium2DHwMLCyPrJjrjc5gF+zLqhZskRib lmwxFNqLSrS371SzTF14CK90Mqd5L8o2QnkGIdJZnzE7AywpJv7v+tPK0hw3yEdh3XdD 1d5x1jUdfO5xp5Tv+m1y/RusQmfB7uBYK87WoRF3M+TK9BtkNv6IZpLLG1i3zfYgiorD wmSWZR7KqQrnNNHQG7h0Apthfb4EimW3axWqLlptZ6LOJO+6X4EiUyoVyQd14fTYGq6q OSYg== X-Gm-Message-State: AOAM533LgkFBHoyO4LVku2meQcYujbmzARp7buZ5/ynyLHmLCjfxauws qywpRJr11IBjGk85m2YW3JaIU1Gml59CNC2A X-Google-Smtp-Source: ABdhPJwysux6giTy3tYdt7Z2nZVkEgydjb+8D1NYocjIh9+yP//sp5gssNrUxfvnhqGcCMQo7PPkzg== X-Received: by 2002:a5d:4e0b:: with SMTP id p11mr9983889wrt.32.1599759541467; Thu, 10 Sep 2020 10:39:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check Date: Thu, 10 Sep 2020 18:38:51 +0100 Message-Id: <20200910173855.4068-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200910173855.4068-1-peter.maydell@linaro.org> References: <20200910173855.4068-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN bit in short-descriptor translation table format descriptors. This is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the feature bit with an ID register check, in line with our preference for ID register checks over feature bits. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 15 ++++++++++++++- target/arm/cpu.c | 1 - target/arm/helper.c | 5 +++-- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a1c7d8ebae5..b7c2615b2fe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1775,6 +1775,15 @@ FIELD(ID_ISAR6, FHM, 8, 4) FIELD(ID_ISAR6, SB, 12, 4) FIELD(ID_ISAR6, SPECRES, 16, 4) =20 +FIELD(ID_MMFR0, VMSA, 0, 4) +FIELD(ID_MMFR0, PMSA, 4, 4) +FIELD(ID_MMFR0, OUTERSHR, 8, 4) +FIELD(ID_MMFR0, SHARELVL, 12, 4) +FIELD(ID_MMFR0, TCM, 16, 4) +FIELD(ID_MMFR0, AUXREG, 20, 4) +FIELD(ID_MMFR0, FCSE, 24, 4) +FIELD(ID_MMFR0, INNERSHR, 28, 4) + FIELD(ID_MMFR3, CMAINTVA, 0, 4) FIELD(ID_MMFR3, CMAINTSW, 4, 4) FIELD(ID_MMFR3, BPMAINT, 8, 4) @@ -1952,7 +1961,6 @@ enum arm_features { ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register = */ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */ ARM_FEATURE_MPIDR, /* has cp15 MPIDR */ - ARM_FEATURE_PXN, /* has Privileged Execute Never bit */ ARM_FEATURE_LPAE, /* has Large Physical Address Extension */ ARM_FEATURE_V8, ARM_FEATURE_AARCH64, /* supports 64 bit mode */ @@ -3618,6 +3626,11 @@ static inline bool isar_feature_aa32_vminmaxnm(const= ARMISARegisters *id) return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 +static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >=3D 4; +} + static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c179e0752da..c5e86ce50af 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1589,7 +1589,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) } if (arm_feature(env, ARM_FEATURE_LPAE)) { set_feature(env, ARM_FEATURE_V7MP); - set_feature(env, ARM_FEATURE_PXN); } if (arm_feature(env, ARM_FEATURE_CBAR_RO)) { set_feature(env, ARM_FEATURE_CBAR); diff --git a/target/arm/helper.c b/target/arm/helper.c index 44d666627a8..ef6eaf6450f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10537,6 +10537,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, target_ulong *page_size, ARMMMUFaultInfo *fi) { CPUState *cs =3D env_cpu(env); + ARMCPU *cpu =3D env_archcpu(env); int level =3D 1; uint32_t table; uint32_t desc; @@ -10563,7 +10564,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, goto do_fault; } type =3D (desc & 3); - if (type =3D=3D 0 || (type =3D=3D 3 && !arm_feature(env, ARM_FEATURE_P= XN))) { + if (type =3D=3D 0 || (type =3D=3D 3 && !cpu_isar_feature(aa32_pxn, cpu= ))) { /* Section translation fault, or attempt to use the encoding * which is Reserved on implementations without PXN. */ @@ -10605,7 +10606,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, pxn =3D desc & 1; ns =3D extract32(desc, 19, 1); } else { - if (arm_feature(env, ARM_FEATURE_PXN)) { + if (cpu_isar_feature(aa32_pxn, cpu)) { pxn =3D (desc >> 2) & 1; } ns =3D extract32(desc, 3, 1); --=20 2.20.1 From nobody Thu May 2 10:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q186sm4603128wma.45.2020.09.10.10.39.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 10:39:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2T22hnWTeC2DUA3syxYlTqgfpNOouUNFsu2vYh7GjxQ=; b=kqLRNhOm6qFvWXYbHP6w2hJGJuBwpcT1ly2UeJh2QxRj9o9FKpxE42YV4NqwFlViK0 U0QX6kv5Nj5WO3ktM+rRa12wxKkTMuJsNusl/KWB/puxU3QSlkHLpVoNglJpRqLzbPaH fF48+mUC8AnY13G72QoROJ9jqcD/SgzmJC2OyOZ+QAZPV+0A6avddNJi2gW9lrRaF4y9 kfTXS9KBZ/8I5Zc1bE03j4shZS0AWbQsUH3tBgL3u/qPtc4HofvbvZNff8R9JumSdzGT 8VC4mw4BKE8/mImTGB9CqNPLL2sohFtYr2tN97fmiMiqCDktCG3MtywfAm+0JQUah2qY vVkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2T22hnWTeC2DUA3syxYlTqgfpNOouUNFsu2vYh7GjxQ=; b=roPWFVmMjqm7/joJaguPq3HWLMj7JJlUaH498smmYR0rhk0SDJy3dc/ruBVnftWjpc fjyYAaTb8KtycxYg7szfjIw514p/nMA3mb5lF1v+YbA7y1ngHKV4EojAEP75lcridQLA ii8gd+C1Tcw63eEdQaolHfVm3TdYNGHSZxburt0/FyUu0FqbDGINb4U4pPiZ00W4v7Z1 09iZMnbDFrmBZRoyVOM4qF7Cr06LJoaqoUfgApbkvscF88Auu5eupjHsaCPVe0DjXiA0 8C3pDYjVaLKIgVh69/nntKpl0Zq6PhPHviB2F2yoJH/cEB+9J/GpjQk0zRgS2smQjz41 lUnQ== X-Gm-Message-State: AOAM532NiOJ2w07o552uSETBB9uhW0bSwkAux/G9OQWbJWmdj45lsh8x U6DYzQNipS0Wbt+G9dN5/LGXuQ== X-Google-Smtp-Source: ABdhPJyJGfXgYb8X3TQKSq7KlSu5AiGkFPwJJO7cjkdHiH7P0uBuR9YuhyC1GHlSisEo8D1mPPSozw== X-Received: by 2002:a1c:a789:: with SMTP id q131mr1067339wme.141.1599759543367; Thu, 10 Sep 2020 10:39:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/5] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters Date: Thu, 10 Sep 2020 18:38:52 +0100 Message-Id: <20200910173855.4068-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200910173855.4068-1-peter.maydell@linaro.org> References: <20200910173855.4068-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters sub-struct. We're going to want id_pfr1 for an isar_features check, and moving both at the same time avoids an odd inconsistency. Changes other than the ones to cpu.h and kvm64.c made automatically with: perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/ar= mv7m_nvic.c Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I haven't changed the kvm32.c code to read the ID_PFR* from the kernel as the comment above ARMISARegisters suggests, because I expect the patchset deleting that file to go in before this one. --- target/arm/cpu.h | 4 ++-- hw/intc/armv7m_nvic.c | 4 ++-- target/arm/cpu.c | 20 ++++++++++---------- target/arm/cpu64.c | 12 ++++++------ target/arm/cpu_tcg.c | 36 ++++++++++++++++++------------------ target/arm/helper.c | 4 ++-- target/arm/kvm64.c | 4 ++++ 7 files changed, 44 insertions(+), 40 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b7c2615b2fe..de2ab41e2a0 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -909,6 +909,8 @@ struct ARMCPU { uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_mmfr4; + uint32_t id_pfr0; + uint32_t id_pfr1; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; @@ -929,8 +931,6 @@ struct ARMCPU { uint32_t reset_fpsid; uint32_t ctr; uint32_t reset_sctlr; - uint32_t id_pfr0; - uint32_t id_pfr1; uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 7876c1ba07e..a28be49c1e9 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1238,9 +1238,9 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) "Aux Fault status registers unimplemented\n"); return 0; case 0xd40: /* PFR0. */ - return cpu->id_pfr0; + return cpu->isar.id_pfr0; case 0xd44: /* PFR1. */ - return cpu->id_pfr1; + return cpu->isar.id_pfr1; case 0xd48: /* DFR0. */ return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c5e86ce50af..a4ea71811e5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1660,7 +1660,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) /* Disable the security extension feature bits in the processor fe= ature * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. */ - cpu->id_pfr1 &=3D ~0xf0; + cpu->isar.id_pfr1 &=3D ~0xf0; cpu->isar.id_aa64pfr0 &=3D ~0xf000; } =20 @@ -1697,7 +1697,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * id_aa64pfr0_el1[11:8]. */ cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->id_pfr1 &=3D ~0xf000; + cpu->isar.id_pfr1 &=3D ~0xf000; } =20 #ifndef CONFIG_USER_ONLY @@ -1895,8 +1895,8 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00011111; cpu->ctr =3D 0x82048004; cpu->reset_sctlr =3D 0x00c50078; - cpu->id_pfr0 =3D 0x1031; - cpu->id_pfr1 =3D 0x11; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x31100003; @@ -1967,8 +1967,8 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x01111111; cpu->ctr =3D 0x80038003; cpu->reset_sctlr =3D 0x00c50078; - cpu->id_pfr0 =3D 0x1031; - cpu->id_pfr1 =3D 0x11; + cpu->isar.id_pfr0 =3D 0x1031; + cpu->isar.id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x00100103; @@ -2031,8 +2031,8 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x84448003; cpu->reset_sctlr =3D 0x00c50078; - cpu->id_pfr0 =3D 0x00001131; - cpu->id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -2076,8 +2076,8 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x11111111; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50078; - cpu->id_pfr0 =3D 0x00001131; - cpu->id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr0 =3D 0x00001131; + cpu->isar.id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3c2b3d95993..e00271b932f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -108,8 +108,8 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->id_pfr0 =3D 0x00000131; - cpu->id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -161,8 +161,8 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x84448004; /* L1Ip =3D VIPT */ cpu->reset_sctlr =3D 0x00c50838; - cpu->id_pfr0 =3D 0x00000131; - cpu->id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10101105; @@ -213,8 +213,8 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; cpu->ctr =3D 0x8444c004; cpu->reset_sctlr =3D 0x00c50838; - cpu->id_pfr0 =3D 0x00000131; - cpu->id_pfr1 =3D 0x00011011; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x10201105; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 00b0e08f33e..a9b7cf52550 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -142,8 +142,8 @@ static void arm1136_r2_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; + cpu->isar.id_pfr0 =3D 0x111; + cpu->isar.id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -173,8 +173,8 @@ static void arm1136_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; + cpu->isar.id_pfr0 =3D 0x111; + cpu->isar.id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -205,8 +205,8 @@ static void arm1176_initfn(Object *obj) cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1dd20d2; cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x11; + cpu->isar.id_pfr0 =3D 0x111; + cpu->isar.id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->isar.id_mmfr0 =3D 0x01130003; @@ -234,8 +234,8 @@ static void arm11mpcore_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x11111111; cpu->isar.mvfr1 =3D 0x00000000; cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; + cpu->isar.id_pfr0 =3D 0x111; + cpu->isar.id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->isar.id_mmfr0 =3D 0x01100103; @@ -266,8 +266,8 @@ static void cortex_m3_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); cpu->midr =3D 0x410fc231; cpu->pmsav7_dregion =3D 8; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -296,8 +296,8 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000000; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00000030; @@ -326,8 +326,8 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x12000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00100030; @@ -358,8 +358,8 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr0 =3D 0x10110021; cpu->isar.mvfr1 =3D 0x11000011; cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000210; + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000210; cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->isar.id_mmfr0 =3D 0x00101F40; @@ -397,8 +397,8 @@ static void cortex_r5_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_PMSA); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->id_pfr0 =3D 0x0131; - cpu->id_pfr1 =3D 0x001; + cpu->isar.id_pfr0 =3D 0x0131; + cpu->isar.id_pfr1 =3D 0x001; cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->isar.id_mmfr0 =3D 0x0210030; diff --git a/target/arm/helper.c b/target/arm/helper.c index ef6eaf6450f..93c1c01267a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6625,7 +6625,7 @@ static void define_pmu_regs(ARMCPU *cpu) static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri) { ARMCPU *cpu =3D env_archcpu(env); - uint64_t pfr1 =3D cpu->id_pfr1; + uint64_t pfr1 =3D cpu->isar.id_pfr1; =20 if (env->gicv3state) { pfr1 |=3D 1 << 28; @@ -7258,7 +7258,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_pfr0 }, + .resetvalue =3D cpu->isar.id_pfr0 }, /* ID_PFR1 is not a plain ARM_CP_CONST because we don't know * the value of the GIC field until after we define these regs. */ diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index ef1e9602850..736be1f236b 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -555,6 +555,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0, + ARM64_SYS_REG(3, 0, 0, 1, 0)); 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id q186sm4603128wma.45.2020.09.10.10.39.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 10:39:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Abb+4aWoXJ2ymPQS9jB6u7hwn1+xp0oekf6hABPJtaQ=; b=R79MhwPCxN3Q8wDVBCpU45GkO6HQcz2yqG8bNl17s+OwgimWGqdRekEmbjnD0YyT9O ++hwNcQhafMLshxvgj6MdJUdMWOKAI0g5QR7dTF88QAGEf2Fz8d0rr21ohbqoT9dbBvK 3Z0JqnHGIoezEs5jW2evuEJH9qcUcfeAhQ+XweZ9JyyJbd+ybY+oz5Jy+Q6ub3Q+KG4e Yv0KfJyZBC7sOlNOiHxjy9w1uU8yPg910aEfKr83LJzadb4lxiaZmve4sGPILMy3NMaU mnXa7wNgGQPykNiV92PN5CDw/rxdyqOgRqzIMS3bBQ8askhoZsKs3+6WZNlPYr3prHf/ ff/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Abb+4aWoXJ2ymPQS9jB6u7hwn1+xp0oekf6hABPJtaQ=; b=CPbvd/I/kCN1UOmL2VlxzD0pzJ45E+KW1FTSBEq22SfGC5sblKLuULG0wZm402kmDn 5ODMmIopRzNX/BIWziC4dABQ3pt+8K3DNUHqaawYqQgrQZE7viwu/HL5mE90qqu5yPwx aS0xcJPIDt1R1SExWtnGMVGr44PnrIY5joYtikbq02ehVBKnRToL8zqNkd9VX1mBTCF+ dS1kwbtd+MDL3Le1elD/2g8DhjzsQlk/NVsxeE72NdWeIMrDoVC71sMBE1YXQx5YN23S eXtF7gcYZcLjQVm2JTScOtkDdog76ZHSbePO2ihC3i6FRZIuHtsKgMIMIm5wTxEVPXJd TT1A== X-Gm-Message-State: AOAM531CzmXAOMDS5dnNH2Mc8ZHneM02/W12HMt5+vhJemKhkzci6ZQO xReWUdbNe3qSvX8ImqIveXPZzg== X-Google-Smtp-Source: ABdhPJylBMY9dUXCn/nOLAc2yX+zuAohqH4YZthtj5g8CFwnvFeYwbUjxbdthNLXFnL3SdNfie7Vjg== X-Received: by 2002:a1c:2086:: with SMTP id g128mr1117098wmg.89.1599759544682; Thu, 10 Sep 2020 10:39:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs Date: Thu, 10 Sep 2020 18:38:53 +0100 Message-Id: <20200910173855.4068-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200910173855.4068-1-peter.maydell@linaro.org> References: <20200910173855.4068-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" M-profile CPUs only implement the ID registers as guest-visible if the CPU implements the Main Extension (all our current CPUs except the Cortex-M0 do). Currently we handle this by having the Cortex-M0 leave the ID register values in the ARMCPU struct as zero, but this conflicts with our design decision to make QEMU behaviour be keyed off ID register fields wherever possible. Explicitly code the ID registers in the NVIC to return 0 if the Main Extension is not implemented, so we can make the M0 model set the ARMCPU struct fields to obtain the correct behaviour without those values becoming guest-visible. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index a28be49c1e9..42b1ad59e65 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1238,32 +1238,74 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) "Aux Fault status registers unimplemented\n"); return 0; case 0xd40: /* PFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_pfr0; case 0xd44: /* PFR1. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_pfr1; case 0xd48: /* DFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->id_afr0; case 0xd50: /* MMFR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr0; case 0xd54: /* MMFR1. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr1; case 0xd58: /* MMFR2. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr2; case 0xd5c: /* MMFR3. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_mmfr3; case 0xd60: /* ISAR0. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar0; case 0xd64: /* ISAR1. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar1; case 0xd68: /* ISAR2. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar2; case 0xd6c: /* ISAR3. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar3; case 0xd70: /* ISAR4. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar4; case 0xd74: /* ISAR5. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) { + goto bad_offset; + } return cpu->isar.id_isar5; case 0xd78: /* CLIDR */ return cpu->clidr; --=20 2.20.1 From nobody Thu May 2 10:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599759733; cv=none; d=zohomail.com; s=zohoarc; b=Joldt9qap0fvAkR3HOc2rQ04MdN4e9pDlRFicfOeoL3glYceIO8EuBAMiD5i+3UqUm72crairqvWyks5q+6lhWg6whAs8DMkkP1+xmO4zAQ0jh3Az+bi4/mVtFPv+EPeZIz5VHKidiBAHZoscXAJ5pzSxNbgRUQ+VFOcJurhXAI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599759733; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QeNzMtOZTYV0IOHCApAJqADotFnerf/bH2WL1EVEpCU=; b=X6vdHllCE1zCO6VPa/4cLrnb9CM5gDgcvyBfx59OgbRXh8p6gwIsANSK+A9DTO94RUrG0+nLompq+SItIZhUiNmEMfB8VsDByLpIOeERqgzwv/BgD8LrTpnUn1BEHI+8Mcmwl8Nk+sdPo4huLYN5MiRREV6nWQlp/nkgM1CCzkg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1599759733078511.998701484912; Thu, 10 Sep 2020 10:42:13 -0700 (PDT) Received: from localhost ([::1]:46114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kGQaJ-0000Xe-NI for importer@patchew.org; Thu, 10 Sep 2020 13:42:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kGQXO-0003wp-2X for qemu-devel@nongnu.org; Thu, 10 Sep 2020 13:39:10 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:36867) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kGQXL-0002o2-5N for qemu-devel@nongnu.org; Thu, 10 Sep 2020 13:39:09 -0400 Received: by mail-wr1-x441.google.com with SMTP id z4so7739304wrr.4 for ; Thu, 10 Sep 2020 10:39:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q186sm4603128wma.45.2020.09.10.10.39.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 10:39:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QeNzMtOZTYV0IOHCApAJqADotFnerf/bH2WL1EVEpCU=; b=V0qLfelhP5Exlq4MjriXLd7sYqS2X3wd9wHutRBM9NAMnn12UFgREvmSOg6XH1E9xq bPLqclF3Ebaaht24FU6/8+gOHefrQ6H5Gi99nMe56O1L7htcY/9FPx9SDzyyXeomomao Yea4bzVTkwLa80apZ3benSWXVS8PbytQ5ERffXMGFaVjaTcj8rGqUFMs0J7D5QZ6J182 DftvUocP2SYa6YXJXwan+XjTh6ZutF7cykObhgR+Z/KsjIDKQowSfGh9zNwX/tSnpcV6 tAWzH0v17X70eRuzY4LigPNduLaPyki1WdK2fYRqnzXVht683q6NWt+zUdLxp5kdWWW2 yGgg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QeNzMtOZTYV0IOHCApAJqADotFnerf/bH2WL1EVEpCU=; b=mGBh3ErO3/vrB+oUG8RHdpiK+Kt+jg3x8HvDfgVa404EX6z4Z7tY24K+xxcbyn8VLB Du9ryizewJEEF+2CMWiOj7Rkx6YxIQ9Glyk6k3g+Dr2pRwXEHWMieUdwVfHwes17mVjn ZF4+lMzyrxMg5+0xWRuFBmxGHYO9+JdgLuoH0XoH4o34g+3QLhDb5fwzohMqrGrXAUZR Xd+KYv4gJJvNgJgcpJuwf5AzvXKEeg0P3CYTtFAEJV2GaqK5IvMb0naKzwopm1pS/r/R VhTtKm3TvUdC8Oco/HK8LHti5IxWCvPMMJMLCjmeknQKCycrwPZJiTA45kudOxsOkBXo ApsA== X-Gm-Message-State: AOAM530ukOIwgBJcNqc5VkEMQuQvGJ1c7JqBwmGfMS+nNg7F9l4XJprt 4k38CTg9CHUI0ygcjdhqxQzCoA== X-Google-Smtp-Source: ABdhPJwaGsdt6HgdztPcu8/KtMr0kxghPrLr+Sk5b5qJDqkaiRJEOJcA+2tQm3O0GNU+JBWF3UbeGw== X-Received: by 2002:adf:dd0b:: with SMTP id a11mr10016798wrm.422.1599759545755; Thu, 10 Sep 2020 10:39:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/5] target/arm: Add ID register values for Cortex-M0 Date: Thu, 10 Sep 2020 18:38:54 +0100 Message-Id: <20200910173855.4068-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200910173855.4068-1-peter.maydell@linaro.org> References: <20200910173855.4068-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Give the Cortex-M0 ID register values corresponding to its implemented behaviour. These will not be guest-visible but will be used to govern the behaviour of QEMU's emulation. We use the same values that the Cortex-M3 does. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index a9b7cf52550..0013e25412f 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -256,6 +256,30 @@ static void cortex_m0_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); =20 cpu->midr =3D 0x410cc200; + + /* + * These ID register values are not guest visible, because + * we do not implement the Main Extension. They must be set + * to values corresponding to the Cortex-M0's implemented + * features, because QEMU generally controls its emulation + * by looking at ID register fields. We use the same values as + * for the M3. + */ + cpu->isar.id_pfr0 =3D 0x00000030; + cpu->isar.id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; } =20 static void cortex_m3_initfn(Object *obj) --=20 2.20.1 From nobody Thu May 2 10:31:53 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599759816; cv=none; d=zohomail.com; s=zohoarc; b=EvZBWU11C7bg03TgxDvKHe5Oo5myybVCMPTlNxtSQb3Ay/8ke7V5VOP4Ec3oMS2U8CdegDpZNYJ2CsWguAvlfOX5WmakGYWH+l20NnY9y/m87stDEsgSnzDyiiyWrWV0WcJtTX7P/gpMtPrZckXv0ZtIgevBeg+XfAz42k6iqvo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599759816; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TGaZ8S9jCTIwlbnlsjzYIzfStZejwdYuXoamg2TI9as=; b=bz/tBNoh/7v3V3scds9SgdYbTxMAiVipDYHsLvyNco+qdiUdO5IfTgKPxzF6X2ldy9c52VCZIeEmyQtQVW7Lw3m8NQ4fspifTRR2H88skL+u7LGcMZ7rjiHI9y96WEwLVm6ysz1MdMtR+2lNGTSkHWvxUd8xSDDUp/yCzChs0vo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1599759815993262.20758317018965; Thu, 10 Sep 2020 10:43:35 -0700 (PDT) Received: from localhost ([::1]:50268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kGQbe-0002Jr-KC for importer@patchew.org; Thu, 10 Sep 2020 13:43:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kGQXO-0003zT-TM for qemu-devel@nongnu.org; Thu, 10 Sep 2020 13:39:10 -0400 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:34257) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kGQXM-0002or-Cz for qemu-devel@nongnu.org; Thu, 10 Sep 2020 13:39:10 -0400 Received: by mail-wm1-x341.google.com with SMTP id c19so2367119wmd.1 for ; Thu, 10 Sep 2020 10:39:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id q186sm4603128wma.45.2020.09.10.10.39.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Sep 2020 10:39:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TGaZ8S9jCTIwlbnlsjzYIzfStZejwdYuXoamg2TI9as=; b=UzRA1BQf0o6Y1LDeUINMQgs3MPqkViM6s8XkifXfjoktbwOhaDXxNzzxCPWG/u+wrN j/p4y8Qj6siyz9u6l0h3wcqnLk+0Hr3A/XVXJH7nnma/bwWxqIPguf96y5RoD1eAGGlP O+hrQc2sUM7J78Mku9S3EYlVvn/oIRvyd0fUBNs2OiHbDcY+whIQU7ZyYbE22Hu+4TRl y6D9qlN/IMPGzS7HONOpYWrk6TEu2HctLyEUssAj/0kR8jb0UGfoF8FUyyjirHmu9XS2 tyUiZTVuQEWX+Igd57fSX4wN/aCNV6PjXJDC6blXcc/Lek9lUUGRwrka3PzqDlqvfxbq 3fBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TGaZ8S9jCTIwlbnlsjzYIzfStZejwdYuXoamg2TI9as=; b=hza7cTo7JPdrbBntrGn4m+8h7mPgjF+sq85cLiqRFQxqUaTDZwlqhiy2OHI5an/nqL B+1TNPlF731DOWwV8t/MTqhetAyrr6hge8EKj4Dn6mX2rv0JqnZv8Jfx9XagR2nfiA4d FVuRrQM/oFRwIpO6DuUY108czdEAcMRD7bmEmlTTQuTZskkwZv87Uq9N8Lo3IdmRNveF eYZBMFGUYW9s8rtbmI59aELNOutXFIVKWqnsPBqegz/qpXj9ZrvYM2fcgRpubzRJM82g CCTrIEJN+Kjfyn6kLlE0TdBGlzX4W8jz14yS+TBksCpOl9UEp1B6zvjVMGT6VjDR3Ntl XgiQ== X-Gm-Message-State: AOAM531iEoG5y5YN6eUvags3Wz5LcDoOycKh8pR3O4OF/8lMXV/uLTEd T1yVrR6m8llAGhha3oQ/VJ+DEDsML7sfqn6l X-Google-Smtp-Source: ABdhPJxIChppOT5/GesOMe6d4y5DK88fvU2htlst5nSn4gCCNg9rviAjxZaJRG3dJ72OSa6o23nEYA== X-Received: by 2002:a1c:ba0b:: with SMTP id k11mr1149719wmf.20.1599759547032; Thu, 10 Sep 2020 10:39:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/5] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile Date: Thu, 10 Sep 2020 18:38:55 +0100 Message-Id: <20200910173855.4068-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200910173855.4068-1-peter.maydell@linaro.org> References: <20200910173855.4068-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::341; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The M-profile definition of the MVFR1 ID register differs slightly from the A-profile one, and in particular the check for "does the CPU support fp16 arithmetic" is not the same. We don't currently implement any M-profile CPUs with fp16 arithmetic, so this is not yet a visible bug, but correcting the logic now disarms this beartrap for when we eventually do. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index de2ab41e2a0..8453808b36d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1802,6 +1802,15 @@ FIELD(ID_MMFR4, LSM, 20, 4) FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) =20 +FIELD(ID_PFR1, PROGMOD, 0, 4) +FIELD(ID_PFR1, SECURITY, 4, 4) +FIELD(ID_PFR1, MPROGMOD, 8, 4) +FIELD(ID_PFR1, VIRTUALIZATION, 12, 4) +FIELD(ID_PFR1, GENTIMER, 16, 4) +FIELD(ID_PFR1, SEC_FRAC, 20, 4) +FIELD(ID_PFR1, VIRT_FRAC, 24, 4) +FIELD(ID_PFR1, GIC, 28, 4) + FIELD(ID_AA64ISAR0, AES, 4, 4) FIELD(ID_AA64ISAR0, SHA1, 8, 4) FIELD(ID_AA64ISAR0, SHA2, 12, 4) @@ -1919,10 +1928,12 @@ FIELD(MVFR0, FPROUND, 28, 4) =20 FIELD(MVFR1, FPFTZ, 0, 4) FIELD(MVFR1, FPDNAN, 4, 4) -FIELD(MVFR1, SIMDLS, 8, 4) -FIELD(MVFR1, SIMDINT, 12, 4) -FIELD(MVFR1, SIMDSP, 16, 4) -FIELD(MVFR1, SIMDHP, 20, 4) +FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */ +FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */ +FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */ +FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */ +FIELD(MVFR1, MVE, 8, 4) /* M-profile only */ +FIELD(MVFR1, FP16, 20, 4) /* M-profile only */ FIELD(MVFR1, FPHP, 24, 4) FIELD(MVFR1, SIMDFMAC, 28, 4) =20 @@ -3525,9 +3536,19 @@ static inline bool isar_feature_aa32_predinv(const A= RMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) !=3D 0; } =20 +static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) !=3D 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { - return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >=3D 3; + /* Sadly this is encoded differently for A-profile and M-profile */ + if (isar_feature_aa32_mprofile(id)) { + return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0; + } else { + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >=3D 3; + } } =20 static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) --=20 2.20.1