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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" There are several ways we can expand a vector dup of a 64-bit element on a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index f9c6450837..507c95cd39 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3954,6 +3954,100 @@ static void tcg_reg_alloc_op(TCGContext *s, const T= CGOp *op) } } =20 +static void tcg_reg_alloc_dup2(TCGContext *s, const TCGOp *op) +{ + const TCGLifeData arg_life =3D op->life; + TCGTemp *ots, *itsl, *itsh; + TCGType vtype =3D TCGOP_VECL(op) + TCG_TYPE_V64; + + /* This opcode is only valid for 32-bit hosts, for 64-bit elements. */ + tcg_debug_assert(TCG_TARGET_REG_BITS =3D=3D 32); + tcg_debug_assert(TCGOP_VECE(op) =3D=3D MO_64); + + ots =3D arg_temp(op->args[0]); + itsl =3D arg_temp(op->args[1]); + itsh =3D arg_temp(op->args[2]); + + /* ENV should not be modified. */ + tcg_debug_assert(!temp_readonly(ots)); + + /* Allocate the output register now. */ + if (ots->val_type !=3D TEMP_VAL_REG) { + TCGRegSet allocated_regs =3D s->reserved_regs; + TCGRegSet dup_out_regs =3D + tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs; + + /* Make sure to not spill the input registers. */ + if (!IS_DEAD_ARG(1) && itsl->val_type =3D=3D TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsl->reg); + } + if (!IS_DEAD_ARG(2) && itsh->val_type =3D=3D TEMP_VAL_REG) { + tcg_regset_set_reg(allocated_regs, itsh->reg); + } + + ots->reg =3D tcg_reg_alloc(s, dup_out_regs, allocated_regs, + op->output_pref[0], ots->indirect_base); + ots->val_type =3D TEMP_VAL_REG; + ots->mem_coherent =3D 0; + s->reg_to_temp[ots->reg] =3D ots; + } + + /* Promote dup2 of immediates to dupi_vec. */ + if (itsl->val_type =3D=3D TEMP_VAL_CONST && itsh->val_type =3D=3D TEMP= _VAL_CONST) { + uint64_t val =3D deposit64(itsl->val, 32, 32, itsh->val); + MemOp vece =3D MO_64; + + if (val =3D=3D dup_const(MO_8, val)) { + vece =3D MO_8; + } else if (val =3D=3D dup_const(MO_16, val)) { + vece =3D MO_16; + } else if (val =3D=3D dup_const(MO_32, val)) { + vece =3D MO_32; + } + + tcg_out_dupi_vec(s, vtype, vece, ots->reg, val); + goto done; + } + + /* If the two inputs form one 64-bit value, try dupm_vec. */ + if (itsl + 1 =3D=3D itsh && + itsl->base_type =3D=3D TCG_TYPE_I64 && + itsh->base_type =3D=3D TCG_TYPE_I64) { + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } + if (!itsl->mem_coherent) { + temp_sync(s, itsl, s->reserved_regs, 0, 0); + } +#ifdef HOST_WORDS_BIGENDIAN + TCGTemp *its =3D itsh; +#else + TCGTemp *its =3D itsl; +#endif + if (tcg_out_dupm_vec(s, vtype, MO_64, ots->reg, + its->mem_base->reg, its->mem_offset)) { + goto done; + } + } + + /* Fall back to generic expansion. */ + tcg_reg_alloc_op(s, op); + return; + + done: + if (IS_DEAD_ARG(1)) { + temp_dead(s, itsl); + } + if (IS_DEAD_ARG(2)) { + temp_dead(s, itsh); + } + if (NEED_SYNC_ARG(0)) { + temp_sync(s, ots, s->reserved_regs, 0, IS_DEAD_ARG(0)); + } else if (IS_DEAD_ARG(0)) { + temp_dead(s, ots); + } +} + #ifdef TCG_TARGET_STACK_GROWSUP #define STACK_DIR(x) (-(x)) #else @@ -4345,6 +4439,9 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) case INDEX_op_dup_vec: tcg_reg_alloc_dup(s, op); break; + case INDEX_op_dup2_vec: + tcg_reg_alloc_dup2(s, op); + break; case INDEX_op_insn_start: if (num_insns >=3D 0) { size_t off =3D tcg_current_code_size(s); --=20 2.25.1