From nobody Mon Feb 9 14:33:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of redhat.com designates 207.211.31.81 as permitted sender) client-ip=207.211.31.81; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-1.mimecast.com; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 207.211.31.81 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1599223301; cv=none; d=zohomail.com; s=zohoarc; b=mr4JmILx5u1yTpOPRM6M4s+b9e2c86VXDpyPzRyXtDVUqFo2WJpwkoBte+kw9R4Y0c4/CxshhOLzwdoN+Yg2CDi9K9xoeeuvNrpIEIDuUpGY/oIIwBDZEH62eJSpVN80CLT/4LJ69RYSMFkYEQaKwkzNKzUWaLGPCyHqwu+1r8g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599223301; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=sb4uXiFvtrqRn/GlqalTIrcUPoERtLqLldrd535gyMg=; b=Cx/90NTrG1/uVwKkAeeIOPDdq0P7GyJcTbPCUgcphBuC0yTtUZzbhAlAT47eO9C6LLDqSdTu/SjZL5NwrqIQ8VXHt/b0luHl3E+Rlopcu7MJVKx0txkvpJUewiUhHyyJO/t9SdLgewEoHC3hnjq5XNHuMsVfUbJW/ubiYasL0s4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of redhat.com designates 207.211.31.81 as permitted sender) smtp.mailfrom=philmd@redhat.com; dmarc=pass header.from= (p=none dis=none) header.from= Received: from us-smtp-delivery-1.mimecast.com (us-smtp-1.mimecast.com [207.211.31.81]) by mx.zohomail.com with SMTPS id 1599223301407441.5387226309688; Fri, 4 Sep 2020 05:41:41 -0700 (PDT) Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-257-UvPTPXaGOKa88yBU3Jd1mQ-1; Fri, 04 Sep 2020 08:41:39 -0400 Received: by mail-wm1-f72.google.com with SMTP id w3so2164370wmg.4 for ; Fri, 04 Sep 2020 05:41:39 -0700 (PDT) Return-Path: Return-Path: Received: from localhost.localdomain (50.red-83-52-54.dynamicip.rima-tde.net. [83.52.54.50]) by smtp.gmail.com with ESMTPSA id 185sm3626889wma.18.2020.09.04.05.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 04 Sep 2020 05:41:37 -0700 (PDT) X-MC-Unique: UvPTPXaGOKa88yBU3Jd1mQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sb4uXiFvtrqRn/GlqalTIrcUPoERtLqLldrd535gyMg=; b=ll53fdiitwe8b0XUhmW9OTiaqXbpQSxhQPnXF2RLFQnXdUirO5c5xZlLdrE3wB49+L 2Z7FlsTC73hJKrOIWBBShin1SfFt3oyImljIecbM0Rsh3kV7rf4IL7Kp4h3RJjBZYo0y iVMc1zUu+WtneO7efJdiyTHeHvj0McXz5n/JVFoMEUzEjyVTBkwcD7M3m7mbQ9u9kpMW JQwU10V/qzTqY1QUsx9uS1c8j4TZvRcB0wJ01cPWLH6GcRotB4bx2pfno6To9NMShrKz ykgsUL9A4wczzdwBCUNthz+sureDkSMNfEt77+uZX5Qip4uiR0JUOK9lllWdqx3bzWMC fPQA== X-Gm-Message-State: AOAM5330ifs+VjJxET2Wai1YSzDCQrVppB/oSOCTrhSELZtmi9p06vrC vzvyWVj+PGaGvr5zOVqhUSq+BnCAxUm3cTI12TS90PFtWzg2ND98mc3z21i+Px6WW5ydtAHQn8o 9T9qq7oqXRhdDlQ== X-Received: by 2002:a1c:6145:: with SMTP id v66mr7792028wmb.171.1599223298259; Fri, 04 Sep 2020 05:41:38 -0700 (PDT) X-Google-Smtp-Source: ABdhPJw2AWjwRNhrOuxy5aVntw74Dd2eAwFLf58CSi/Y0Z9nEHjuMs6mZ20121sSBuFKRE61s1PTuw== X-Received: by 2002:a1c:6145:: with SMTP id v66mr7792003wmb.171.1599223298008; Fri, 04 Sep 2020 05:41:38 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Klaus Jensen , qemu-block@nongnu.org, Kevin Wolf , Fam Zheng , Keith Busch , Stefan Hajnoczi , Max Reitz , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 1/3] block/nvme: Group controller registers in NVMeRegs structure Date: Fri, 4 Sep 2020 14:41:28 +0200 Message-Id: <20200904124130.583838-2-philmd@redhat.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200904124130.583838-1-philmd@redhat.com> References: <20200904124130.583838-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0.002 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable We want to use the NvmeBar structure from "block/nvme.h" in the next commit. As a preliminary step, group all the NVMe controller registers in the 'ctrl' field, keeping the doorbells registers out of it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- block/nvme.c | 48 +++++++++++++++++++++++++----------------------- 1 file changed, 25 insertions(+), 23 deletions(-) diff --git a/block/nvme.c b/block/nvme.c index 24e6e7f0866..c9c3fc02fed 100644 --- a/block/nvme.c +++ b/block/nvme.c @@ -83,21 +83,23 @@ typedef struct { =20 /* Memory mapped registers */ typedef volatile struct { - uint64_t cap; - uint32_t vs; - uint32_t intms; - uint32_t intmc; - uint32_t cc; - uint32_t reserved0; - uint32_t csts; - uint32_t nssr; - uint32_t aqa; - uint64_t asq; - uint64_t acq; - uint32_t cmbloc; - uint32_t cmbsz; - uint8_t reserved1[0xec0]; - uint8_t cmd_set_specfic[0x100]; + struct { + uint64_t cap; + uint32_t vs; + uint32_t intms; + uint32_t intmc; + uint32_t cc; + uint32_t reserved0; + uint32_t csts; + uint32_t nssr; + uint32_t aqa; + uint64_t asq; + uint64_t acq; + uint32_t cmbloc; + uint32_t cmbsz; + uint8_t reserved1[0xec0]; + uint8_t cmd_set_specfic[0x100]; + } ctrl; uint32_t doorbells[]; } NVMeRegs; =20 @@ -734,7 +736,7 @@ static int nvme_init(BlockDriverState *bs, const char *= device, int namespace, /* Perform initialize sequence as described in NVMe spec "7.6.1 * Initialization". */ =20 - cap =3D le64_to_cpu(s->regs->cap); + cap =3D le64_to_cpu(s->regs->ctrl.cap); if (!(cap & (1ULL << 37))) { error_setg(errp, "Device doesn't support NVMe command set"); ret =3D -EINVAL; @@ -747,10 +749,10 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, timeout_ms =3D MIN(500 * ((cap >> 24) & 0xFF), 30000); =20 /* Reset device to get a clean state. */ - s->regs->cc =3D cpu_to_le32(le32_to_cpu(s->regs->cc) & 0xFE); + s->regs->ctrl.cc =3D cpu_to_le32(le32_to_cpu(s->regs->ctrl.cc) & 0xFE); /* Wait for CSTS.RDY =3D 0. */ deadline =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + timeout_ms * SCA= LE_MS; - while (le32_to_cpu(s->regs->csts) & 0x1) { + while (le32_to_cpu(s->regs->ctrl.csts) & 0x1) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to reset (%" PRId64 " ms)", @@ -771,18 +773,18 @@ static int nvme_init(BlockDriverState *bs, const char= *device, int namespace, } s->nr_queues =3D 1; QEMU_BUILD_BUG_ON(NVME_QUEUE_SIZE & 0xF000); - s->regs->aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE_SIZE= ); - s->regs->asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); - s->regs->acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); + s->regs->ctrl.aqa =3D cpu_to_le32((NVME_QUEUE_SIZE << 16) | NVME_QUEUE= _SIZE); + s->regs->ctrl.asq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->sq.iova); + s->regs->ctrl.acq =3D cpu_to_le64(s->queues[INDEX_ADMIN]->cq.iova); =20 /* After setting up all control registers we can enable device now. */ - s->regs->cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | + s->regs->ctrl.cc =3D cpu_to_le32((ctz32(NVME_CQ_ENTRY_BYTES) << 20) | (ctz32(NVME_SQ_ENTRY_BYTES) << 16) | 0x1); /* Wait for CSTS.RDY =3D 1. */ now =3D qemu_clock_get_ns(QEMU_CLOCK_REALTIME); deadline =3D now + timeout_ms * 1000000; - while (!(le32_to_cpu(s->regs->csts) & 0x1)) { + while (!(le32_to_cpu(s->regs->ctrl.csts) & 0x1)) { if (qemu_clock_get_ns(QEMU_CLOCK_REALTIME) > deadline) { error_setg(errp, "Timeout while waiting for device to start (%" PRId64 " ms)", --=20 2.26.2