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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p14sm7285023wrg.96.2020.09.03.13.20.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 13:20:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hOtqBYNVN0odFdezyYG5pn2QHUjOmA1+K/WZY0tpkq0=; b=TpfXSgm2WUu6IzjPY75GkWOL2vzKGMJmWRX43OVD7HGwwccWmAYhVPQl061kqcaWYP jglUYwgrFbxrY7nyEK+0rdysMQZJQFwTmD0AA/h0Idq3WJl3btgcrOmSh2aQsF0m73ok 32PUKsP1QE5Uh6fyPIC1YxO+oQJOA3ppyLBVGyj1R9wAgBc2c7xkb/BQcO1Jqf9oJce5 GzJYSqkn+0u8OuWLpJMhJLKzT9DFj5+vcCj0ngEcvRIYZkHu6uiOaMtOTFFgzQFbbEP9 3RRER364g1wzWs3ZiuA+2oqobPVxmPYrAOwDaKxHM2cm2NJNcthE3lMPR6GqaSQN085d aTBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hOtqBYNVN0odFdezyYG5pn2QHUjOmA1+K/WZY0tpkq0=; b=GHjnhiDZYFm28pvcgVXjbwNwQAX/6eahH32lBpTdkWuMrOnDkaWu4JAm/2JFOyaNWE csqR55ZgerZ6w4jOMwZy8MOd2WU9evvtpYT0Fw1MYigck+7W+hmcOWXKDVpyeIlKXhkD dDU2ya6zul6fuoav4v2blsOQEJG6xRFXuXCM9DRpYBuY/o86kDQBsTTdWb2Mj1YFNb5T VVQw0Tf/m9B5TmGve8lRQsmSe8GHAwL1vdtkZG6Y4dIH8LTb/rg8bK5ZNFG2Y1LtXnly 7wkNQ4umxaPJ3jjbD3lnQQt2xc+BDyXUfLCdi3X0iNE9q+qnxhM8nWIJuRvc9FivD0vR 3slA== X-Gm-Message-State: AOAM533kq1ujPrHk3wApTApuaUCQPs5+BblbCwf6AGSqcj5lKTLwovzY DXH3KLV5F+9u+CV0WZSzmtpwAg== X-Google-Smtp-Source: ABdhPJziafnF1rxURkGDV/L7i1tyNJs3klFneSeHLtA+KcUm4xSSaF5KHQOwQV6nvM6az+qniP9NnA== X-Received: by 2002:a1c:408a:: with SMTP id n132mr3977627wma.45.1599164452304; Thu, 03 Sep 2020 13:20:52 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/3] hw/arm/mps2: New board model mps2-an386 Date: Thu, 3 Sep 2020 21:20:46 +0100 Message-Id: <20200903202048.15370-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200903202048.15370-1-peter.maydell@linaro.org> References: <20200903202048.15370-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Implement a model of the MPS2 with the AN386 firmware. This is essentially identical to the AN385 firmware, but it has a Cortex-M4 rather than a Cortex-M3. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- The docs update is new since v1, but I've kept the Reviewed-bys as there is no code change. --- docs/system/arm/mps2.rst | 8 +++++--- hw/arm/mps2.c | 30 +++++++++++++++++++++++++++--- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 3a98cb59b0d..e680a4ceb71 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an505``, ``mps2-an511``, ``mps2-an= 521``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an= 511``, ``mps2-an521``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models all use Arm M-profile CPUs. =20 @@ -12,6 +12,8 @@ QEMU models the following FPGA images: =20 ``mps2-an385`` Cortex-M3 as documented in ARM Application Note AN385 +``mps2-an386`` + Cortex-M4 as documented in ARM Application Note AN386 ``mps2-an511`` Cortex-M3 'DesignStart' as documented in AN511 ``mps2-an505`` @@ -21,7 +23,7 @@ QEMU models the following FPGA images: =20 Differences between QEMU and real hardware: =20 -- AN385 remapping of low 16K of memory to either ZBT SSRAM1 or to +- AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to block RAM is unimplemented (QEMU always maps this to ZBT SSRAM1, as if zbt_boot_ctrl is always zero) - QEMU provides a LAN9118 ethernet rather than LAN9220; the only guest diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 9f12934ca8f..559b297e788 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -15,6 +15,7 @@ * as seen by the guest depend significantly on the FPGA image. * We model the following FPGA images: * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 + * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 * * Links to the TRM for the board itself and to the various Application @@ -47,6 +48,7 @@ =20 typedef enum MPS2FPGAType { FPGA_AN385, + FPGA_AN386, FPGA_AN511, } MPS2FPGAType; =20 @@ -79,6 +81,7 @@ typedef struct { =20 #define TYPE_MPS2_MACHINE "mps2" #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") +#define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386") #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") =20 #define MPS2_MACHINE(obj) \ @@ -142,7 +145,7 @@ static void mps2_common_init(MachineState *machine) * * Common to both boards: * 0x21000000..0x21ffffff : PSRAM (16MB) - * AN385 only: + * AN385/AN386 only: * 0x00000000 .. 0x003fffff : ZBT SSRAM1 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 @@ -157,7 +160,7 @@ static void mps2_common_init(MachineState *machine) * 0x20000000 .. 0x2001ffff : SRAM * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 * - * The AN385 has a feature where the lowest 16K can be mapped + * The AN385/AN386 has a feature where the lowest 16K can be mapped * either to the bottom of the ZBT SSRAM1 or to the block RAM. * This is of no use for QEMU so we don't implement it (as if * zbt_boot_ctrl is always zero). @@ -166,6 +169,7 @@ static void mps2_common_init(MachineState *machine) =20 switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400= 000); make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); @@ -193,6 +197,7 @@ static void mps2_common_init(MachineState *machine) armv7m =3D DEVICE(&mms->armv7m); switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: @@ -229,6 +234,7 @@ static void mps2_common_init(MachineState *machine) =20 switch (mmc->fpga_type) { case FPGA_AN385: + case FPGA_AN386: { /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. @@ -380,7 +386,7 @@ static void mps2_common_init(MachineState *machine) */ lan9118_init(&nd_table[0], 0x40200000, qdev_get_gpio_in(armv7m, - mmc->fpga_type =3D=3D FPGA_AN385 ? 13 : = 47)); + mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 system_clock_scale =3D NANOSECONDS_PER_SECOND / SYSCLK_FRQ; =20 @@ -409,6 +415,17 @@ static void mps2_an385_class_init(ObjectClass *oc, voi= d *data) mmc->scc_id =3D 0x41043850; } =20 +static void mps2_an386_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS2 with AN386 FPGA image for Cortex-M4"; + mmc->fpga_type =3D FPGA_AN386; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); + mmc->scc_id =3D 0x41043860; +} + static void mps2_an511_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -435,6 +452,12 @@ static const TypeInfo mps2_an385_info =3D { .class_init =3D mps2_an385_class_init, }; =20 +static const TypeInfo mps2_an386_info =3D { + .name =3D TYPE_MPS2_AN386_MACHINE, + .parent =3D TYPE_MPS2_MACHINE, + .class_init =3D mps2_an386_class_init, +}; + static const TypeInfo mps2_an511_info =3D { .name =3D TYPE_MPS2_AN511_MACHINE, .parent =3D TYPE_MPS2_MACHINE, @@ -445,6 +468,7 @@ static void mps2_machine_init(void) { type_register_static(&mps2_info); type_register_static(&mps2_an385_info); + type_register_static(&mps2_an386_info); type_register_static(&mps2_an511_info); } =20 --=20 2.20.1 From nobody Sun May 5 17:56:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599164566; cv=none; d=zohomail.com; s=zohoarc; b=EwDuODN+XArrUDLLvaSnPlHwo4vhmErWrNvbdcWNwLS5DZB3Ps/16Xnp1i4A6zFFiDA216zJYxvNQ9Zm1US0A7q66nZFrB9TcYV0lcSRoG+sbVycyylR00Be3A51Jw6nfSjr5X1MlymKn+PIHufGRRk2HjnzrH7ex+ZHoYnCS+I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599164566; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6lxmtVJqPBkLqKbE78/o4FRZ58Zm5BvzP8WeZTcTIuI=; b=ZhrD1ujNHNqIX8W1zV+v5nr/sk+ZJvdj1PUiY8Az0RdLVMtbXX0lDaVIfW86VORRKi0UuReATOUkghG3x4R/nejSC0hBh6btg0CZmubzNmgkdG6NJDKdwb6uv0JLVxmLkMwolEG8T0nMuop4Jo6Cm1d+rIwNrzc33N6+E4l8uVg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1599164566025966.8155013213527; Thu, 3 Sep 2020 13:22:46 -0700 (PDT) Received: from localhost ([::1]:49754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kDvkr-0007t1-3l for importer@patchew.org; Thu, 03 Sep 2020 16:22:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kDvj7-0006DI-HR for qemu-devel@nongnu.org; Thu, 03 Sep 2020 16:20:57 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:36763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kDvj5-000857-4H for qemu-devel@nongnu.org; Thu, 03 Sep 2020 16:20:57 -0400 Received: by mail-wm1-x32f.google.com with SMTP id z9so4126335wmk.1 for ; Thu, 03 Sep 2020 13:20:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p14sm7285023wrg.96.2020.09.03.13.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 13:20:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6lxmtVJqPBkLqKbE78/o4FRZ58Zm5BvzP8WeZTcTIuI=; b=uNtqnTNxnFyzjT1YD14dEEjpqstSy/DvooVquH7314K6lY+wnfeU13ahIR/PjDNdNd S4cFHNAOJzeOSPaT/CNPFh7l8nR4KhVOR4dEiCjZ1LgzabDRJ0T70rsX/ibr0tehiURk cZgtjFksL6tG7UdT8sNRYjZGFlI2v9VsmM67vaHotErmRwRx2FeTiasvpV3s1LcACrG2 ExVhfKPvg/SLlSSbmEzOrzmTD6mdsFtomLdje+0oLf5MsDoAsmoWnd+0T8kzLBz+xRvu f5FOOniJugxAsqpnLXe7fIPw6vL9fHkSbH6MasfaH/Cb943SnkXw0G4a1KR83/FH/vKo FDwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6lxmtVJqPBkLqKbE78/o4FRZ58Zm5BvzP8WeZTcTIuI=; b=T50JVQAn7W8yobtIIVoLbeAbA2b+/VJVG2768Z4A8vMr1evB4LJraY6pRRlxKxbun6 mpn57SuCUzgwZh6DMDqc5Oj0pm77rE0Mch9OQkWVEoBYC+G08g/MdK0AGl6IHQVnYqC7 OdoijgARpLiA7Z3+V8B3qP57YWDc6bty1RXmzy2BMbxFdrVC9TR13RJ4GmBAadUcBab/ Yl62uPOskmhwsIMUYlCnJnlPTbbhlxhm55UA4PmTFuCEEN/ZJWt+tkVpWRGz1FajDlpf xqhiWaxy75jXBXAVAtbJkvQr0AWfaCpQfj8fOBLJ8AsfEeOPkvTKMD3VA3nk9MBArxIq y6ZA== X-Gm-Message-State: AOAM532eqmAt7OcH8nqlrFECrGLm9gd9FQjDhYkeln1ifd4dlWw44pkA J7czrjjnUGu5xs8mR7eA8JtGJg== X-Google-Smtp-Source: ABdhPJx16W2JKSkjZsdT+LWndv9hWuEUHEJcJXQeNAg+pKtXCRTxZncOGJZOBmRjS4WMUhCPz3X0UQ== X-Received: by 2002:a1c:7c1a:: with SMTP id x26mr4366907wmc.112.1599164453778; Thu, 03 Sep 2020 13:20:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 2/3] hw/arm/mps2: New board model mps2-an500 Date: Thu, 3 Sep 2020 21:20:47 +0100 Message-Id: <20200903202048.15370-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200903202048.15370-1-peter.maydell@linaro.org> References: <20200903202048.15370-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Implement a model of the MPS2 with the AN500 firmware. This is similar to the AN385, with the following differences: * Cortex-M7 CPU * PSRAM is at 0x6000_0000 * Ethernet is at 0xa000_0000 * No zbt_boot_ctrl remapping of the low 16K (but QEMU doesn't implement this anyway) * no "block RAM" at 0x01000000 Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- The AN500 also defines some behaviour for CFG_REG[2567] in the SCC (QEMU hw/misc/mps2-scc.c) but none of it is anything QEMU can conveniently support so I have left that code as-is (a guest accessing those registers will hit the LOG_GUEST_ERROR case for "bad offset"). Tested with a buildroot image created using the instructions at: https://community.arm.com/developer/tools-software/oss-platforms/w/docs/57= 8/running-uclinux-on-the-arm-mps2-platform and the "arm_mps2_CM7fpga" defconfig; QEMU commandline is qemu-system-arm -M mps2-an500 -serial stdio -display none -kernel boot.axf= -device loader,file=3Dlinux.axf --- docs/system/arm/mps2.rst | 6 ++-- hw/arm/mps2.c | 71 ++++++++++++++++++++++++++++++++-------- 2 files changed, 62 insertions(+), 15 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index e680a4ceb71..7f2e9c8d52e 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -1,5 +1,5 @@ -Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an505``, ``mps2-an= 511``, ``mps2-an521``) -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Arm MPS2 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an= 505``, ``mps2-an511``, ``mps2-an521``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =20 These board models all use Arm M-profile CPUs. =20 @@ -14,6 +14,8 @@ QEMU models the following FPGA images: Cortex-M3 as documented in ARM Application Note AN385 ``mps2-an386`` Cortex-M4 as documented in ARM Application Note AN386 +``mps2-an500`` + Cortex-M7 as documented in ARM Application Note AN500 ``mps2-an511`` Cortex-M3 'DesignStart' as documented in AN511 ``mps2-an505`` diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c index 559b297e788..d17fd7a7cb5 100644 --- a/hw/arm/mps2.c +++ b/hw/arm/mps2.c @@ -16,6 +16,7 @@ * We model the following FPGA images: * "mps2-an385" -- Cortex-M3 as documented in ARM Application Note AN385 * "mps2-an386" -- Cortex-M4 as documented in ARM Application Note AN386 + * "mps2-an500" -- Cortex-M7 as documented in ARM Application Note AN500 * "mps2-an511" -- Cortex-M3 'DesignStart' as documented in AN511 * * Links to the TRM for the board itself and to the various Application @@ -49,6 +50,7 @@ typedef enum MPS2FPGAType { FPGA_AN385, FPGA_AN386, + FPGA_AN500, FPGA_AN511, } MPS2FPGAType; =20 @@ -56,6 +58,9 @@ typedef struct { MachineClass parent; MPS2FPGAType fpga_type; uint32_t scc_id; + bool has_block_ram; + hwaddr ethernet_base; + hwaddr psram_base; } MPS2MachineClass; =20 typedef struct { @@ -82,6 +87,7 @@ typedef struct { #define TYPE_MPS2_MACHINE "mps2" #define TYPE_MPS2_AN385_MACHINE MACHINE_TYPE_NAME("mps2-an385") #define TYPE_MPS2_AN386_MACHINE MACHINE_TYPE_NAME("mps2-an386") +#define TYPE_MPS2_AN500_MACHINE MACHINE_TYPE_NAME("mps2-an500") #define TYPE_MPS2_AN511_MACHINE MACHINE_TYPE_NAME("mps2-an511") =20 #define MPS2_MACHINE(obj) \ @@ -143,13 +149,14 @@ static void mps2_common_init(MachineState *machine) * tradeoffs. For QEMU they're all just RAM, though. We arbitrarily * call the 16MB our "system memory", as it's the largest lump. * - * Common to both boards: - * 0x21000000..0x21ffffff : PSRAM (16MB) - * AN385/AN386 only: + * AN385/AN386/AN511: + * 0x21000000 .. 0x21ffffff : PSRAM (16MB) + * AN385/AN386/AN500: * 0x00000000 .. 0x003fffff : ZBT SSRAM1 * 0x00400000 .. 0x007fffff : mirror of ZBT SSRAM1 * 0x20000000 .. 0x203fffff : ZBT SSRAM 2&3 * 0x20400000 .. 0x207fffff : mirror of ZBT SSRAM 2&3 + * AN385/AN386 only: * 0x01000000 .. 0x01003fff : block RAM (16K) * 0x01004000 .. 0x01007fff : mirror of above * 0x01008000 .. 0x0100bfff : mirror of above @@ -159,22 +166,17 @@ static void mps2_common_init(MachineState *machine) * 0x00400000 .. 0x007fffff : ZBT SSRAM1 * 0x20000000 .. 0x2001ffff : SRAM * 0x20400000 .. 0x207fffff : ZBT SSRAM 2&3 + * AN500 only: + * 0x60000000 .. 0x60ffffff : PSRAM (16MB) * * The AN385/AN386 has a feature where the lowest 16K can be mapped * either to the bottom of the ZBT SSRAM1 or to the block RAM. * This is of no use for QEMU so we don't implement it (as if * zbt_boot_ctrl is always zero). */ - memory_region_add_subregion(system_memory, 0x21000000, machine->ram); + memory_region_add_subregion(system_memory, mmc->psram_base, machine->r= am); =20 - switch (mmc->fpga_type) { - case FPGA_AN385: - case FPGA_AN386: - make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); - make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400= 000); - make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); - make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", - &mms->ssram23, 0x20400000); + if (mmc->has_block_ram) { make_ram(&mms->blockram, "mps.blockram", 0x01000000, 0x4000); make_ram_alias(&mms->blockram_m1, "mps.blockram_m1", &mms->blockram, 0x01004000); @@ -182,6 +184,17 @@ static void mps2_common_init(MachineState *machine) &mms->blockram, 0x01008000); make_ram_alias(&mms->blockram_m3, "mps.blockram_m3", &mms->blockram, 0x0100c000); + } + + switch (mmc->fpga_type) { + case FPGA_AN385: + case FPGA_AN386: + case FPGA_AN500: + make_ram(&mms->ssram1, "mps.ssram1", 0x0, 0x400000); + make_ram_alias(&mms->ssram1_m, "mps.ssram1_m", &mms->ssram1, 0x400= 000); + make_ram(&mms->ssram23, "mps.ssram23", 0x20000000, 0x400000); + make_ram_alias(&mms->ssram23_m, "mps.ssram23_m", + &mms->ssram23, 0x20400000); break; case FPGA_AN511: make_ram(&mms->blockram, "mps.blockram", 0x0, 0x40000); @@ -198,6 +211,7 @@ static void mps2_common_init(MachineState *machine) switch (mmc->fpga_type) { case FPGA_AN385: case FPGA_AN386: + case FPGA_AN500: qdev_prop_set_uint32(armv7m, "num-irq", 32); break; case FPGA_AN511: @@ -235,6 +249,7 @@ static void mps2_common_init(MachineState *machine) switch (mmc->fpga_type) { case FPGA_AN385: case FPGA_AN386: + case FPGA_AN500: { /* The overflow IRQs for UARTs 0, 1 and 2 are ORed together. * Overflow for UARTs 4 and 5 doesn't trigger any interrupt. @@ -384,7 +399,7 @@ static void mps2_common_init(MachineState *machine) /* In hardware this is a LAN9220; the LAN9118 is software compatible * except that it doesn't support the checksum-offload feature. */ - lan9118_init(&nd_table[0], 0x40200000, + lan9118_init(&nd_table[0], mmc->ethernet_base, qdev_get_gpio_in(armv7m, mmc->fpga_type =3D=3D FPGA_AN511 ? 47 : = 13)); =20 @@ -413,6 +428,9 @@ static void mps2_an385_class_init(ObjectClass *oc, void= *data) mmc->fpga_type =3D FPGA_AN385; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); mmc->scc_id =3D 0x41043850; + mmc->psram_base =3D 0x21000000; + mmc->ethernet_base =3D 0x40200000; + mmc->has_block_ram =3D true; } =20 static void mps2_an386_class_init(ObjectClass *oc, void *data) @@ -424,6 +442,23 @@ static void mps2_an386_class_init(ObjectClass *oc, voi= d *data) mmc->fpga_type =3D FPGA_AN386; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m4"); mmc->scc_id =3D 0x41043860; + mmc->psram_base =3D 0x21000000; + mmc->ethernet_base =3D 0x40200000; + mmc->has_block_ram =3D true; +} + +static void mps2_an500_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + MPS2MachineClass *mmc =3D MPS2_MACHINE_CLASS(oc); + + mc->desc =3D "ARM MPS2 with AN500 FPGA image for Cortex-M7"; + mmc->fpga_type =3D FPGA_AN500; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m7"); + mmc->scc_id =3D 0x41045000; + mmc->psram_base =3D 0x60000000; + mmc->ethernet_base =3D 0xa0000000; + mmc->has_block_ram =3D false; } =20 static void mps2_an511_class_init(ObjectClass *oc, void *data) @@ -435,6 +470,9 @@ static void mps2_an511_class_init(ObjectClass *oc, void= *data) mmc->fpga_type =3D FPGA_AN511; mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-m3"); mmc->scc_id =3D 0x41045110; + mmc->psram_base =3D 0x21000000; + mmc->ethernet_base =3D 0x40200000; + mmc->has_block_ram =3D false; } =20 static const TypeInfo mps2_info =3D { @@ -458,6 +496,12 @@ static const TypeInfo mps2_an386_info =3D { .class_init =3D mps2_an386_class_init, }; =20 +static const TypeInfo mps2_an500_info =3D { + .name =3D TYPE_MPS2_AN500_MACHINE, + .parent =3D TYPE_MPS2_MACHINE, + .class_init =3D mps2_an500_class_init, +}; + static const TypeInfo mps2_an511_info =3D { .name =3D TYPE_MPS2_AN511_MACHINE, .parent =3D TYPE_MPS2_MACHINE, @@ -469,6 +513,7 @@ static void mps2_machine_init(void) type_register_static(&mps2_info); type_register_static(&mps2_an385_info); type_register_static(&mps2_an386_info); + type_register_static(&mps2_an500_info); type_register_static(&mps2_an511_info); } =20 --=20 2.20.1 From nobody Sun May 5 17:56:03 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1599164624; cv=none; d=zohomail.com; s=zohoarc; b=cfj8pu/i4EpcpQwGDJxdOAlt0vgtMYxWZCnfd3Qf2kNWf9QrFQk8YncgSZgRjQvoDzwg633I5cyctrd78FLGgdw0sIMRPIjxRSckukHpfY+4jhvY52maUsuj64gBRE8yDyxS+Zu4TGCj4kOBle/190ISFIgwaVOPIxsC6eNzK7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599164624; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cAXCKGC6VbvlDmQ7gtrKURJrxX8tvf9unlVaP2aE39c=; b=nui0EZ1IQOzlnJbMtWXmi1kPHGIPLeb/YrGlYbRqZUTGZnHdamdisU1Fg1H763gEuCvegFRP5VLJyCmYVjJ14DlVk6//o4EcXmZafvYjEGiW3Xm+Nurkf9dohaNBKVj1lgSKh/0v94mftFpKcL9uEUjp9XPEeLRfa3A7dv9zfAY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 159916462463296.44624044094655; Thu, 3 Sep 2020 13:23:44 -0700 (PDT) Received: from localhost ([::1]:54544 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kDvlm-0001O6-S0 for importer@patchew.org; Thu, 03 Sep 2020 16:23:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:41396) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kDvj7-0006EF-Tx for qemu-devel@nongnu.org; Thu, 03 Sep 2020 16:20:57 -0400 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:41033) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kDvj6-00085J-4x for qemu-devel@nongnu.org; Thu, 03 Sep 2020 16:20:57 -0400 Received: by mail-wr1-x444.google.com with SMTP id w5so4549786wrp.8 for ; Thu, 03 Sep 2020 13:20:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p14sm7285023wrg.96.2020.09.03.13.20.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Sep 2020 13:20:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cAXCKGC6VbvlDmQ7gtrKURJrxX8tvf9unlVaP2aE39c=; b=pw6ju/X3lBFbTFamqIZYwJnw6UGjyzawXYbBlpmmrV8aNUHdz9LHdf5N0cvyHIAvOw MwTtdkO42RuTV51u0RH3IeCPiMU8ijrOUIpjKXG0LXcf4uHZjpGwvoHgZcf3sQBlX4Jj /lUvTm2+lw4OJXeEdO2itLDNLjyQ7dalndm4e4+q5PmqjrIk2BS0kudPm4di/qmxRJEg 9kcJpZV68k1sWzX0GFvUK3zT8w5RN+H56R+C1KYORnOtOSmGyRf+N95F6ZXyP7KVJLku E4J8F/bk9t235GZcJMwRjx1q88oiTfsj8tY3yH9xm9YJzxrUeNEFb9HktSfU1/S8RzsS Ri6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cAXCKGC6VbvlDmQ7gtrKURJrxX8tvf9unlVaP2aE39c=; b=iL+HzkKGPs/lA51abvBpMJJirlgNzlDGbTEiBqEUrFESj/b/dEZ5dxR7H45oFq0xJT NePKNTw/95TXE/LZiY9YFZx9wrp37YKU1ittFUxEK101MX/dsJSxPcqidiiMXNYilcEk Euf14FjpWUi0sDxyh9L5SXNLy1YbrWQ5XuZSgJ7qe2Yy3FOBDpcT5ad4XMlYalyu7Fl9 +glucbucoWIP5TUB0HoF1MlYjmHEgSVOWslbCsEbe+riFxAVGZzdo4eNj2TrQtRSpFbp HWrn+GbTYT2r5mHgODM+s9N2qpbfCrSBiLVrllKNq4ETIRoXkq3hlZJok+0+3yZGIO5e ze8w== X-Gm-Message-State: AOAM531m1/ZyFWkyMaKN2UY613cbL1KC749v7tjt8yhULvXJhPVJsVq2 vhoUHkrna7y9VezMyuhp1+nOAQ== X-Google-Smtp-Source: ABdhPJxIGAN3pAeVfdbR20vNKGZLdfN9gKVwURb5u3+enOhEq5cahbjBJKQ1ZzPfmAPp6UdIWErlpQ== X-Received: by 2002:adf:8187:: with SMTP id 7mr4243412wra.266.1599164454877; Thu, 03 Sep 2020 13:20:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 3/3] docs/system/arm/mps2.rst: Make board list consistent Date: Thu, 3 Sep 2020 21:20:48 +0100 Message-Id: <20200903202048.15370-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200903202048.15370-1-peter.maydell@linaro.org> References: <20200903202048.15370-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kumar Gala , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Make the list of MPS2 boards consistent in the phrasing of each entry, use the correct casing of "Arm", and move the mps2-an511 entry so the list is in numeric order. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- docs/system/arm/mps2.rst | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst index 7f2e9c8d52e..8c5b5f1fe07 100644 --- a/docs/system/arm/mps2.rst +++ b/docs/system/arm/mps2.rst @@ -11,17 +11,17 @@ as seen by the guest depend significantly on the FPGA i= mage. QEMU models the following FPGA images: =20 ``mps2-an385`` - Cortex-M3 as documented in ARM Application Note AN385 + Cortex-M3 as documented in Arm Application Note AN385 ``mps2-an386`` - Cortex-M4 as documented in ARM Application Note AN386 + Cortex-M4 as documented in Arm Application Note AN386 ``mps2-an500`` - Cortex-M7 as documented in ARM Application Note AN500 -``mps2-an511`` - Cortex-M3 'DesignStart' as documented in AN511 + Cortex-M7 as documented in Arm Application Note AN500 ``mps2-an505`` - Cortex-M33 as documented in ARM Application Note AN505 + Cortex-M33 as documented in Arm Application Note AN505 +``mps2-an511`` + Cortex-M3 'DesignStart' as documented in Arm Application Note AN511 ``mps2-an521`` - Dual Cortex-M33 as documented in Application Note AN521 + Dual Cortex-M33 as documented in Arm Application Note AN521 =20 Differences between QEMU and real hardware: =20 --=20 2.20.1