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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The VCMLA and VCADD insns have a size field which is 0 for fp16 and 1 for fp32 (note that this is the reverse of the Neon 3-same encoding!). Convert it to MO_* values in decode for consistency. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/neon-shared.decode | 18 ++++++++++++------ target/arm/translate-neon.c.inc | 22 ++++++++++++---------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode index f297ba8cdfc..a9d010880d4 100644 --- a/target/arm/neon-shared.decode +++ b/target/arm/neon-shared.decode @@ -34,11 +34,17 @@ %vd_dp 22:1 12:4 %vd_sp 12:4 22:1 =20 -VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +# For VCMLA/VCADD insns, convert the single-bit size field +# which is 0 for fp16 and 1 for fp32 into a MO_* constant. +# (Note that this is the reverse of the sense of the 1-bit size +# field in the 3same_fp Neon insns.) +%vcadd_size 20:1 !function=3Dplus1 =20 -VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VCMLA 1111 110 rot:2 . 1 . .... .... 1000 . q:1 . 0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp size=3D%vcadd_size + +VCADD 1111 110 rot:1 1 . 0 . .... .... 1000 . q:1 . 0 .... \ + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp size=3D%vcadd_size =20 # VUDOT and VSDOT VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \ @@ -51,9 +57,9 @@ VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1= .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp q=3D1 =20 VCMLA_scalar 1111 1110 0 . rot:2 .... .... 1000 . q:1 index:1 0 vm:4 \ - vn=3D%vn_dp vd=3D%vd_dp size=3D0 + vn=3D%vn_dp vd=3D%vd_dp size=3D1 VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp size=3D1 index=3D0 + vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp size=3D2 index=3D0 =20 VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.= inc index 213c1c2174a..4d1a292981b 100644 --- a/target/arm/translate-neon.c.inc +++ b/target/arm/translate-neon.c.inc @@ -168,7 +168,7 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) gen_helper_gvec_3_ptr *fn_gvec_ptr; =20 if (!dc_isar_feature(aa32_vcma, s) - || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { + || (a->size =3D=3D MO_16 && !dc_isar_feature(aa32_fp16_arith, s)))= { return false; } =20 @@ -187,8 +187,9 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D fpstatus_ptr(a->size =3D=3D 0 ? FPST_STD_F16 : FPST_STD); - fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcmlas : gen_helper_gvec_fcm= lah; + fpst =3D fpstatus_ptr(a->size =3D=3D MO_16 ? FPST_STD_F16 : FPST_STD); + fn_gvec_ptr =3D (a->size =3D=3D MO_16) ? + gen_helper_gvec_fcmlah : gen_helper_gvec_fcmlas; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), @@ -205,7 +206,7 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) gen_helper_gvec_3_ptr *fn_gvec_ptr; =20 if (!dc_isar_feature(aa32_vcma, s) - || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) { + || (a->size =3D=3D MO_16 && !dc_isar_feature(aa32_fp16_arith, s)))= { return false; } =20 @@ -224,8 +225,9 @@ static bool trans_VCADD(DisasContext *s, arg_VCADD *a) } =20 opr_sz =3D (1 + a->q) * 8; - fpst =3D fpstatus_ptr(a->size =3D=3D 0 ? FPST_STD_F16 : FPST_STD); - fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fca= ddh; + fpst =3D fpstatus_ptr(a->size =3D=3D MO_16 ? FPST_STD_F16 : FPST_STD); + fn_gvec_ptr =3D (a->size =3D=3D MO_16) ? + gen_helper_gvec_fcaddh : gen_helper_gvec_fcadds; tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), @@ -307,7 +309,7 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_VCM= LA_scalar *a) if (!dc_isar_feature(aa32_vcma, s)) { return false; } - if (a->size =3D=3D 0 && !dc_isar_feature(aa32_fp16_arith, s)) { + if (a->size =3D=3D MO_16 && !dc_isar_feature(aa32_fp16_arith, s)) { return false; } =20 @@ -325,10 +327,10 @@ static bool trans_VCMLA_scalar(DisasContext *s, arg_V= CMLA_scalar *a) return true; } =20 - fn_gvec_ptr =3D (a->size ? gen_helper_gvec_fcmlas_idx - : gen_helper_gvec_fcmlah_idx); + fn_gvec_ptr =3D (a->size =3D=3D MO_16) ? + gen_helper_gvec_fcmlah_idx : gen_helper_gvec_fcmlas_idx; opr_sz =3D (1 + a->q) * 8; - fpst =3D fpstatus_ptr(a->size =3D=3D 0 ? FPST_STD_F16 : FPST_STD); + fpst =3D fpstatus_ptr(a->size =3D=3D MO_16 ? FPST_STD_F16 : FPST_STD); tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd), vfp_reg_offset(1, a->vn), vfp_reg_offset(1, a->vm), --=20 2.20.1